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Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090

178/1731 DocID018909 Rev 11

6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

LTD

CRST

Reserved

SAI1

RST

SPI6

RST

SPI5

RST

Res.

TIM11

RST

TIM10

RST

TIM9

RST

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reser-

ved

SYSCF

G RST

SPI4

RST

SPI1

RST

SDIO

RST

Reserved

ADC

RST

Reserved

USART

RST

USART

RST

Reserved

TIM8

RST

TIM1

RST

rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 LTDCRST: LTDC reset

This bit is set and reset by software.

0: does not reset LCD-TFT

1: resets LCD-TFT

Bits 27:23 Reserved, must be kept at reset value.

Bit 22 SAI1RST: SAI1 reset

This bit is set and reset by software.

0: does not reset SAI1

1: resets SAI1

Bit 21 SPI6RST: SPI6 reset