DocID018909 Rev 11 1541/1731
RM0090 Flexible static memory controller (FSMC)
1588
Figure 435. Mode1 write accesses
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
Table 221. FSMC_BCRx bit fields
Bit
number
Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW 0x0 (no effect on asynchronous mode)
18:16 CPSIZE 0x0 (no effect on asynchronous mode)
15 ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep at
0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect on asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 WRAPMOD 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5-4 MWID As needed
A[25:0]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven by FSMC
ai15558
1HCLK
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