DocID018909 Rev 11 357/1731
RM0090 Chrom-Art Accelerator™ controller (DMA2D)
372
11.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR)
Address offset: 0x0008
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CCEIF CCTCIF CAECIF CTWIF CTCIF CTEIF
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:6 Reserved, must be kept at reset value
Bit 5 CCEIF: Clear configuration error interrupt flag
Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
Bit 3 CAECIF: Clear CLUT access error interrupt flag
Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
Bit 2 CTWIF: Clear transfer watermark interrupt flag
Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
Bit 1 CTCIF: Clear transfer complete interrupt flag
Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
Bit 0 CTEIF: Clear Transfer error interrupt flag
Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
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