DocID018909 Rev 11 1683/1731
RM0090 Debug support (DBG)
1701
38.8.6 SW-AP registers
Access to these registers are initiated when APnDP=1
There are many AP Registers (see AHB-AP) addressed as the combination of:
• The shifted value A[3:2]
• The current value of the DP SELECT register
38.9 AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP
Features:
• System access is independent of the processor status.
• Either SW-DP or JTAG-DP accesses AHB-AP.
• The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the
data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode
bus.
• Bitband transactions are supported.
• AHB-AP transactions bypass the FPB.
The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
c) Bits [7:4] = the bits [7:4] APBANKSEL of the DP SELECT register
d) Bits [3:2] = the 2 address bits of A[3:2] of the 35-bit packet request for SW-DP.
The AHB-AP of the Cortex
®
-M4 with FPU includes 9 x 32-bits registers:
10 Write - SELECT
The purpose is to select the current access
port and the active 4-words register window
11 Read/Write -
READ
BUFFER
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
transaction).
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction
Table 300. SW-DP registers (continued)
A[3:2] R/W
CTRLSEL bit
of SELECT
register
Register Notes
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