DocID018909 Rev 11 147/1731
RM0090 Power controller (PWR)
149
5.5.2 PWR power control/status register (PWR_CSR)
for STM32F42xxx and STM32F43xxx
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
UDRDY[1:0]
ODSWRDY ODRDY
rc_w1 rc_w1 r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res
VOS
RDY
Reserved
BRE EWUP
Reserved.
BRR PVDO SBF WUF
rrwrwrrrr
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 UDRDY[1:0]: Under-drive ready flag
These bits are set by hardware when the Under-drive mode is enabled in Stop mode and
cleared by programming them to 1.
00: Under-drive is disabled
01: Reserved
10: Reserved
11:Under-drive mode is activated in Stop mode.
Bit 17 ODSWRDY: Over-drive mode switching ready
0: Over-drive mode is not active.
1: Over-drive mode is active on digital area on 1.2 V domain
Bit 16 ODRDY: Over-drive mode ready
0: Over-drive mode not ready.
1: Over-drive mode ready
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
0: Not ready
1: Ready
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BRE: Backup regulator enable
When set, the Backup regulator (used to maintain backup SRAM content in Standby and
V
BAT
modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup
SRAM can still be used but its content will be lost in the Standby and V
BAT
modes. Once set,
the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
the data written into the RAM will be maintained in the Standby and V
BAT
modes.
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
or by a power reset.
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