STMicroelectronics STM32F407 User Manual

DocID018909 Rev 11 1391/1731
RM0090 USB on-the-go high-speed (OTG_HS)
1529
Device-mode CSR map
These registers must be programmed every time the core changes to peripheral mode.
OTG_HS_HCCHARx
0x500
0x520
...
0x6E0
OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx)
(x = 0..11, where x = Channel_number) on page 1424
OTG_HS_HCSPLTx 0x504
OTG_HS host channel-x split control register (OTG_HS_HCSPLTx)
(x = 0..11, where x = Channel_number) on page 1426
OTG_HS_HCINTx 0x508
OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11,
where x = Channel_number) on page 1427
OTG_HS_HCINTMSKx 0x50C
OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx)
(x = 0..11, where x = Channel_number) on page 1428
OTG_HS_HCTSIZx 0x510
OTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx)
(x = 0..11, where x = Channel_number) on page 1429
OTG_HS_HCDMAx 0x514
OTG_HS host channel-x DMA address register (OTG_HS_HCDMAx)
(x = 0..11, where x = Channel_number) on page 1430
Table 204. Host-mode control and status registers (CSRs) (continued)
Acronym
Offset
address
Register name
Table 205. Device-mode control and status registers
Acronym
Offset
address
Register name
OTG_HS_DCFG 0x800
OTG_HS device configuration register (OTG_HS_DCFG) on
page 1430
OTG_HS_DCTL 0x804 OTG_HS device control register (OTG_HS_DCTL) on page 1432
OTG_HS_DSTS 0x808 OTG_HS device status register (OTG_HS_DSTS) on page 1434
OTG_HS_DIEPMSK 0x810
OTG_HS device IN endpoint common interrupt mask register
(OTG_HS_DIEPMSK) on page 1435
OTG_HS_DOEPMSK 0x814
OTG_HS device OUT endpoint common interrupt mask register
(OTG_HS_DOEPMSK) on page 1436
OTG_HS_DAINT 0x818
OTG_HS device all endpoints interrupt register (OTG_HS_DAINT)
on page 1437
OTG_HS_DAINTMSK 0x81C
OTG_HS all endpoints interrupt mask register
(OTG_HS_DAINTMSK) on page 1437
OTG_HS_DVBUSDIS 0x828
OTG_HS device VBUS discharge time register
(OTG_HS_DVBUSDIS) on page 1438
OTG_HS_DVBUSPULSE 0x82C
OTG_HS device VBUS pulsing time register
(OTG_HS_DVBUSPULSE) on page 1438
OTG_HS_DIEPEMPMSK 0x834
OTG_HS device IN endpoint FIFO empty interrupt mask register:
(OTG_HS_DIEPEMPMSK) on page 1440

STMicroelectronics STM32F407 Specifications

General

Brand	STMicroelectronics
Model	STM32F407
Category	Controller
Language	English