STMicroelectronics STM32F407 User Manual

Inter-integrated circuit (I
2
C) interface RM0090
844/1731 DocID018909 Rev 11
Note: For each frequency range, the constraint is given based on the worst case which is the
minimum frequency of the range. Greater DNF values can be used if the system can
support maximum hold time violation.
27.3.6 SDA/SCL line control
• If clock stretching is enabled:
– Transmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low
before transmission to wait for the microcontroller to write the byte in the Data
Register (both buffer and shift register are empty).
– Receiver mode: If RxNE=1 and BTF=1: the interface holds the clock line low after
reception to wait for the microcontroller to read the byte in the Data Register (both
buffer and shift register are full).
• If clock stretching is disabled in Slave mode:
– Overrun Error in case of RxNE=1 and no read of DR has been done before the
next byte is received. The last received byte is lost.
– Underrun Error in case TxE=1 and no write into DR has been done before the next
byte must be transmitted. The same byte will be sent again.
– Write Collision not managed.
27.3.7 SMBus
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on
I
2
C
principles of operation. SMBus provides a control bus for system and power management
related tasks. A system may use SMBus to pass messages to and from devices instead of
toggling individual control lines.
The System Management Bus Specification refers to three types of devices. A slave is a
device that is receiving or responding to a command. A master is a device that issues
commands, generates the clocks, and terminates the transfer. A host is a specialized
master that provides the main interface to the system's CPU. A host must be a master-slave
and must support the SMBus host notify protocol. Only one host is allowed in a system.
Similarities between SMBus and I
2
C
• 2 wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional
• Master-slave communication, Master provides clock
• Multi master capability
• SMBus data format similar to I
2
C 7-bit addressing format (Figure 238).
30 < F
PCLK1
<= 40 15 13
40 < F
PCLK1
<= 50 15 15
Table 121. Maximum DNF[3:0] value to be compliant with Thd:dat(max) (continued)
PCLK1 frequency
Maximum DNF value
Sm mode Fm mode

STMicroelectronics STM32F407 Specifications

General

Brand	STMicroelectronics
Model	STM32F407
Category	Controller
Language	English