STMicroelectronics STM32F407 User Manual

DocID018909 Rev 11 1353/1731
RM0090 USB on-the-go full-speed (OTG_FS)
1368
Figure 404 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB
and describes the events involved in the process.
Figure 404. Bulk OUT transaction
After a SetConfiguration/SetInterface command, the application initializes all OUT endpoints
by setting CNAK = 1 and EPENA = 1 (in OTG_FS_DOEPCTLx), and setting a suitable
XFRSIZ and PKTCNT in the OTG_FS_DOEPTSIZx register.
1. host attempts to send data (OUT token) to an endpoint.
2. When the core receives the OUT token on the USB, it stores the packet in the RxFIFO
because space is available there.
3. After writing the complete packet in the RxFIFO, the core then asserts the RXFLVL
interrupt (in OTG_FS_GINTSTS).
4. On receiving the PKTCNT number of USB packets, the core internally sets the NAK bit
for this endpoint to prevent it from receiving any more packets.
5. The application processes the interrupt and reads the data from the RxFIFO.
6. When the application has read all the data (equivalent to XFRSIZ), the core generates
an XFRC interrupt (in OTG_FS_DOEPINTx).
7. The application processes the interrupt and uses the setting of the XFRC interrupt bit
(in OTG_FS_DOEPINTx) to determine that the intended transfer is complete.
IN data transfers
• Packet write
This section describes how the application writes data packets to the endpoint FIFO when
dedicated transmit FIFOs are enabled.
1. The application can either choose the polling or the interrupt mode.
init_out_ep
Host DeviceUSB
O
U
T
A
C
K
RXFLVL intr i
wr_reg(DOEPTSIZx)
wr_reg(DOEPCTLx)
64 bytes
O
U
T
N
A
K
xact _1
Application
XFRC
i
n
t
r
D
O
E
P
C
T
L
x
.
N
A
K
=
1
PKTCNT
0
XFRSIZ = 0
r
idle until intr
rcv_out _pkt()
idle until intr
On new xfer
or RxFIFO
not empty
1
2
3
4
5
6
7
8
XFRSIZ
= 64 bytes
PKTCNT = 1
EPENA = 1
CNAK = 1
ai15679b

STMicroelectronics STM32F407 Specifications

General

Brand	STMicroelectronics
Model	STM32F407
Category	Controller
Language	English