DocID018909 Rev 11 361/1731
RM0090 Chrom-Art Accelerator™ controller (DMA2D)
372
Bit 5 START: Start
This bit can be set to start the automatic loading of the CLUT. It is automatically reset:
– at the end of the transfer
– when the transfer is aborted by the user application by setting the ABORT bit in
DMA2D_CR
– when a transfer error occurs
– when the transfer has not started due to a configuration error or another
transfer operation already ongoing (data transfer or automatic background
CLUT transfer).
Bit 4 CCM: CLUT color mode
This bit defines the color format of the CLUT. It can only be written when the transfer is
disabled. Once the CLUT transfer has started, this bit is read-only.
0: ARGB8888
1: RGB888
others: meaningless
Bits 3:0 CM[3: 0]: Color mode
These bits defines the color format of the foreground image. They can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
others: meaningless
To Next Page
Loading...
Need help?
General
