Contents RM0090
14/1731 DocID018909 Rev 11
14.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
14.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
14.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
14.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 442
14.4.2 Independent trigger with single LFSR generation . . . . . . . . . . . . . . . . 443
14.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 443
14.4.4 Independent trigger with single triangle generation . . . . . . . . . . . . . . . 444
14.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 444
14.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
14.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 445
14.4.8 Simultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 445
14.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 445
14.4.10 Simultaneous trigger with single triangle generation . . . . . . . . . . . . . . 446
14.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 446
14.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
14.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
14.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 450
14.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
14.5.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
14.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
14.5.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
14.5.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
14.5.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
14.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
14.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
14.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
14.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 454
14.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 454
14.5.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
14.5.15 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
To Next Page
Loading...
Need help?
General
