STMicroelectronics STM32F407 - Page 1717

DocID018909 Rev 11 1717/1731
RM0090 Revision history
1726
15-May-2014 7
Embedded Flash memory interface:
Updated Section : Physical remap in STM32F42xxx and
STM32F43xxx. Updated bank 2 selection in Section 2.4: Boot
configuration. Updated notes related to MERx and SER bits in
Section : Mass Erase. Updated Section 3.7.5: Proprietary code
readout protection (PCROP). Updated FLASH_OPTCR register
reset value for STM32F42/43xx in Section 3.9.10: Flash option
control register (FLASH_OPTCR) for STM32F42xxx and
STM32F43xxx and Section 3.9.11: Flash option control register
(FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx.
RCC (STM32F42/43xx):
Updated PPLN caution note in Section 6.3.2: RCC PLL configuration
register (RCC_PLLCFGR)
SYSCFG
Updated MEM_MODE in Section 9.3.1: SYSCFG memory remap
register (SYSCFG_MEMRMP)
LTDC:
Changed resolution do XGA (1024x768) in Section 16.2: LTDC main
features, Section 16.4.1: LTDC Global configuration parameters, and
updated Section 16.7.3: LTDC Active Width Configuration Register
(LTDC_AWCR).
RTC
Added note in Section 26.3.14: Calibration clock output.
TIMER 1/8:
Removed note related to IC1F bits in Section 17.4.7: TIM1&TIM8
capture/compare mode register 1 (TIMx_CCMR1),
TIM2 to 5:
Replaced IC2S by CC2S.
Updated Figure 161: Output stage of capture/compare channel
(channel 1). Removed note related to IC1F bits in Section 18.4.7:
TIMx capture/compare mode register 1 (TIMx_CCMR1).
TIM9 to 14:
Removed note related to IC1F bits in Section 19.5.5: TIM10/11/13/14
capture/compare mode register 1 (TIMx_CCMR1).
USB OTG-HS:
Updated DSPD definition in Section : OTG_HS device configuration
register (OTG_HS_DCFG).
FSMC
Updated DATLAT bits definition in Section : SRAM/NOR-Flash chip-
select timing registers 1..4 (FSMC_BTR1..4).
Table 310. Document revision history (continued)
Date Version Changes