Hardware Interfaces
D-13
B5 -5 VDC -5 volt power
B6 DRQ2 Out DMA request 2
B7 -12 VDC -12 volt power
B8 NOWS_L Out No wait state
B9 +12 VDC +12 volt power
B10 GND In/Out Ground
B11 SMWT_L In System memory write
B12 SMRD_L In System memory read
B13 IOW_L In I/O write
B14 IOR_L In I/O read
B15 DAK3_L In DMA acknowledge 3
B16 DRQ3 Out DMA request 3
B17 DAK1_L In DMA acknowledge 1
B18 DRQ1 Out DMA request 1
B19 REFRESH_L In/Out DRAM refresh control
B20 BCLK In Bus clock
B21 IRQ7 Out Interrupt request 7
B22 IRQ6 Out Interrupt request 6
B23 IRQ5 Out Interrupt request 5
B24 IRQ4 Out Interrupt request 4
B25 IRQ3 Out Interrupt request 3
B26 DAK2_L In DMA acknowledge 2
B27 TC In Terminal count
B28 BALE In Bus address latch enable
B29 +5 VDC +5 volt power
B30 OSC In System oscillator
B31 GND In/Out Ground
C1 SBHE_L In System bus high enable
Table D-9 ISA Bus Pin Definition (continued)
Pin Signal In/Out Description