D300529 0115 - BL67 I/O modules
12-7
BL67-1RS232
STATRES 0-1 This bit is set to reset the STAT bit in the process input data.
With the change from 1 to 0 the STAT bit is reset (from 0 to 1).
If this bit is 0, all changes in TX_BYTE_CNT, TX_CNT and
RX_CNT_ACK are ignored. The clearing of the receive and transmit
buffer by RXBUF FLUSH/TXBUF FLUSH is possible.
The value 1 or the transition from 0 to 1 disables the clearing of the
receive and transmit buffer by the RXBUF FLUSH/TXBUF FLUSH.
RXBUF FLUSH 0 - 1 The RXBUF FLUSH bit is used for clearing the receive buffer.
If STATRES = 1:
A request with RXBUF FLUSH = 1 will be ignored.
If STATRES = 0:
RXBUF FLUSH = 1 will clear the receive buffer.
TXBUF FLUSH 0-1 The TXBUF FLUSH bit is used for clearing the transmit buffer.
If STATRES = 1:
A request with TXBUF FLUSH = 1 will be ignored.
If STATRES = 0:
TXBUF FLUSH = 1 will clear the transmit buffer.
TXBufDis 0-1 Setting this bit deactivates the sending of the TX buffer.
The bit can be used as control bit for actively triggering the sending
of the TX data buffer.
Table 12-2:
Process output
data
Designation Value Description
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