D300529 0115 - BL67 I/O modules
12-33
BL67-1SSI
STS_UFLW 0 A comparison of the register contents has produced the
following result: (REG_SSI_POS) ≥ (REG_LOWER_LIMIT)
1 A comparison of the register contents has produced the
following result: (REG_SSI_POS) < (REG_LOWER_LIMIT)
STS_OFLW 0 A comparison of the register contents has produced the
following result:
(REG_SSI_POS) ≤ (REG_UPPER_LIMIT)
1 A comparison of the register contents has produced the
following result:
(REG_SSI_POS) > (REG_UPPER_LIMIT)
ERR_SSI 0 SSI encoder signal present.
1 SSI encoder signal faulty (e.g. due to a cable break).
SSI_DIAG 0 No enabled status signal is active (SSI_STSx = 0).
1 At least one enabled status signal is active (SSI_STSx = 1)
STS_UP (LED UP) 0 The SSI encoder values are decremented or the values are
constant.
1 The SSI encoder values are incremented.
STS_DN (LED DN) 0 The SSI encoder values are incremented or the values are
constant.
1 The SSI encoder values are decremented.
REL_CMP2 0 A comparison of the register contents has produced the
following result:
(REG_SSI_POS) < (REG_CMP2)
1 A comparison of the register contents has produced the
following result:
(REG_SSI_POS) ≥ (REG_CMP2)
FLAG_CMP2 0 Default status, i.e. the register contents have not yet
matched (REG_SSI_POS) = (REG_CMP2) since the last reset.
1 The contents of the registers match (REG_SSI_POS) =
(REG_CMP2).
This marker must be reset with CLR_CMP2 = 1 in the pro-
cess output data.
STS_CMP2 0 A comparison of the register contents has produced the
following result:
(REG_SSI_POS) ≠ (REG_CMP2)
1 A comparison of the register contents has produced the
following result:
(REG_ SSI_POS) = (REG_CMP2)
Table 12-1:
Meaning of the
data bits (process
input)
Designation Value Description
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