D300529 0115 - BL67 I/O modules
12-37
BL67-1SSI
CLR_CMP1 0 Default status, i.e. reset of FLAG_CMP1 not active.
1 Reset of FLAG_CMP1 active.
EN_CMP1 0 Default status, i.e. the data bits REL_CMP1, STS_CMP1 and
FLAG_CMP1 always have the value 0, irrespective of the
actual SSI encoder value.
1 Comparison active, i.e. the data bits REL_CMP1, STS_CMP1
and FLAG_CMP1 always have a value based on the result of
the comparison with the SSI encoder value.
REG_WR 0 Default status, i.e. there is no request to overwrite the con-
tent of the register with the address stated at
REG_WR_ADR with REG_WR_DATA. Bit REG_WR_AKN
(→ chapter process input (PZDE)") is reset (0).
1 Request to overwrite the content of the register with
address REG_WR_ADR with REG_WR_DATA.
REG_RD_ADR 0…63 Address of the register which has to be read. If the reading
was successful (REG_RD_ABORT = 0), the user data can be
found in REG_RD_DATA in the status interface (bytes 4-7).
REG_WR_DATA 0 bis
2
32
-1
Value which has to be written to the register with the
address REG_WR_ADR.
Table 12-2:
Meaning of the
data bits (process
output)
Designation Value Description
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