Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-25
Example:
If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however,
when the binary representations are added in the destination location using standard binary arithmetic.
If the result of the addition is stored in Register 5FH, the statement:
DA 5FH
Op Code: 40 5F
adjusts this result so the correct BCD representation is obtained.
Register 5F now contains the value 42H. The C, Z, and S Flags are cleared, and V is undefined.
Example:
If addition is performed using the BCD value 15 and 27, the result should be 42. The sum is incorrect, however,
when the binary representations are added in the destination location using standard binary arithmetic.
Register 45F contains the value 5FH, and the result of the addition is stored in Register 5FH, the statement:
DA @45H
Op Code: 40 45
adjusts this result so the correct BCD representation is obtained.
Register 5F now contains the value 42H. The C, Z, and S Flags are cleared, and V is undefined.
0001 0101 = 15H
+0010 0111 = 27H
0011 1100 = 3CH
0011 1100 = 3CH
0000 0110 = 06H
0100 0010 = 42H
0001 0101 = 15H
+ 0010 0111 = 27H
0011 1100 = 3CH
0011 1100 = 3CH
0000 0110 = 06H
0100 0010 = 42H