Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-27
DECW
DECREMENT WORD
DECW
Decrement Word
DECW dst
Instruction Format:
Operation:
dst <— dst - 1
The contents of the destination (which must be an even address) operand are decremented by one. The destination
operand can be a Register Pair or a Working Register Pair.
Note:
Address modes RR or IR can be used to specify a 4-bit Working Register Pair. In this format, the destination
Working Register Pair operand is specified by adding 1110B (EH) to the high nibble of the operand. For example,
if Working Register Pair R12 (CH) is the destination operand, then ECH will be used as the destination operand in
the Op Code.
Example:
If Register Pair 30H and 31H contain the value 0AF2H, the statement:
DECW 30H
Op Code: 80 30
leaves the value 0AF1H in Register Pair 30H and 31H. The Z, V, and S Flags are cleared.
Example:
If Working Register R0 contains 30H and Register Pairs 30H and 31H contain the value FAF3H, the statement:
DECW @R0
Op Code: 81 E0
leaves the value FAF2H in Register Pair 30H and 31H. The S Flag is set, and the Z and V Flags are cleared.
Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise
S: Set if the result of bit 7 is set (negative); cleared otherwise
V: Set if arithmetic overflow occurs; cleared otherwise
D: Unaffected
H: Unaffected
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