Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-75
TM
TEST UNDER MASK
TM
Test Under Mask
TM dst, src
Instruction Format:
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a 0 logical value. The bits to be tested are specified
by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TM instruction ANDs the
destination operand with the source operand (the mask). The Zero (Z) Flag can then be checked to determine the
result. If the Z Flag is set, then the tested bits were 0. When the TM operation is complete, the destination and source
operands still contain their original values.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Example:
If Working Register R3 contains 45H (01000101B) and Working Register R7 contains the value 02H (00000010B)
(bit 1 is being tested if it is 0), the statement:
TM R3, R7
Op Code: 72 37
will set the Z Flag indicating bit 1 in the destination operand is 0. The V and S Flags are cleared.
Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to 0.
D: Unaffected
H: Unaffected
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