ZiLOG Z8 - Page 214

Z8 Microcontrollers
Instruction Descriptions and Formats ZiLOG
12-74 UM001601-0803
TCM
TEST COMPLEMENT UNDER MASK
Example:
If Working Register R3 contains 45H (01000101B) and Working Register R7 contains the value 01H (00000001B)
(bit 0 is being tested if it is 1), the statement:
TCM R3, R7
Op Code: 62 37
will set the Z Flag indicating bit 0 in the destination operand is 1. The V and S Flags are cleared.
Example:
If Working Register R14 contains the value F3H (11110011B), Working Register R5 contains CBH, and Register
CBH contains 88H (10001000B) (bit 7 and bit 3 are being tested if they are 1), the statement:
TCM R14, @R5
Op Code: 63 E5
will reset the Z Flag, because bit 3 in the destination operand is not a 1. The V and S Flags are also cleared.
Example:
If Register D4H contains the value 04H (000001000B), and Working Register R0 contains the value 80H
(10000000B) (bit 7 is being tested if it is 1), the statement:
TCM D4H, R0
Op Code: 64 E0 D4
will reset the Z Flag, because bit 7 in the destination operand is not a 1. The S Flag will be set, and the V Flag will
be cleared.
Example:
If Register DFH contains the value FFH (11111111B), Register 07H contains the value 1FH, and Register 1FH
contains the value BDH (10111101B) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they are 1), the
statement:
TCM DFH, @07H
Op Code: 65 07 DF
will set the Z Flag indicating the tested bits in the destination operand are 1. The S and V Flags are cleared.
Example:
If Working Register R13 contains the value F2H (11110010B), the statement:
TCM R13, #02H
Op Code: 66 ED, 02
tests bit 1 of the destination operand for 1. The Z Flag will be set indicating bit 1 in the destination operand was 1.
The S and V Flags are cleared.
Example:
If Register 5DH contains A0H, and Register A0H contains 0FH (00001111B), the statement:
TCM @5D, #10H
Op Code: 67 5D 10
tests bit 4 of the Register A0H for 1. The Z Flag will be reset indicating bit 1 in the destination operand was not 1.
The S and V Flags are cleared.