Z8 Microcontrollers
ZiLOG Instruction Descriptions and Formats
UM001601-0803 12-73
TCM
TEST COMPLEMENT UNDER MASK
TCM
Test Complement Under Mask
TCM dst, src
Instruction Format:
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified
by setting a 1 bit in the corresponding bit position in the source operand (the mask). The TCM instruction
complements the destination operand, and then ANDs it with the source mask (operand). The Zero (Z) Flag can
then be checked to determine the result. If the Z Flag is set, then the tested bits were 1. When the TCM operation
is complete, the destination and source operands still contain their original values.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or destination
Working Register operand is specified by adding 1110B (EH) to the high nibble of the operand. For example, if
Working Register R12 (CH) is the destination operand, then ECH will be used as the destination operand in the Op
Code.
Flags: C: Unaffected
Z: Set if the result is zero; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to 0.
D: Unaffected
H: Unaffected
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