Z8 Microcontrollers
Reset—Watch-Dog Timer ZiLOG
4-4 UM001601-0803
4.2 RESET PIN, INTERNAL POR OPERATION (Continued)
Table 4-3. Sample Expanded Register File Bank C Reset Values
Register Register Bits
(HEX) Name 7 6 5 4 3 2 1 0 Comments
00 SPI Compare 0 0 0 0 0 0 0 0
(SCOMP)
01 Receive Buffer U U U U U U U U
(RxBUF)
02 SPI Control U U U U 0 0 0 0
(SCON)
Tab le 4-4. Sample Expanded Register File Bank F Reset Values
Register Register Bits
(HEX) Name 7 6 5 4 3 2 1 0 Comments
00 Port Configuration 1 1 1 1 1 1 1 0 Comparator outputs disabled on Port 3
(PCON) Port 0 and 1 output is push-pull
Port 0, 1, 2, 3, and oscillator with standard output
drive
0B STOP-Mode Recovery 0 0 1 0 0 0 0 0 Clock divide by 16 off
(SMR) XTAL divide by 2
POR and / OR External Reset
Stop delay on
Stop recovery level is low, STOP flag is POR
0F Watch-Dog Timer
Mode (WDTMR) U U U 0 1 1 0 1 512 TPC for WDT time out, WDT runs during
STOP
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