ABB Relion 670 series - Page 503

When definite time delay is selected the function will operate as shown in figure 251.
Detailed information about individual stage reset/operation behavior is shown in figure
252 and figure 253 respectively. Note that by setting tResetn = 0.0s, instantaneous reset
of the definite time delayed stage is ensured.
a<b
a
b
Pickup1
V
TRST1
PU_ST1
AND
0
t1
tReset1
0
R
ANSI09000785-3-en.vsd
ANSI09000785 V3 EN
Figure 251: Detailed logic diagram for step 1, DT operation
Pickup1
PU_ST1
TRST1
tReset1
t1
ANSI10000039-3-en.vsd
ANSI10000039 V3 EN
Figure 252: Example for Definite Time Delay stage1 reset
1MRK505222-UUS C Section 8
Voltage protection
497
Technical reference manual