ARM Cortex A9 User Manual

Contents
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. v
ID073015 Non-Confidential
A.2 Reset signals ........................................................................................................... A-3
A.3 Interrupts ................................................................................................................. A-4
A.4 Configuration signals ............................................................................................... A-5
A.5 WFE and WFI standby signals ................................................................................ A-6
A.6 Power management signals .................................................................................... A-7
A.7 AXI interfaces .......................................................................................................... A-8
A.8 Performance monitoring signals ............................................................................ A-14
A.9 Exception flags signal ............................................................................................ A-17
A.10 Parity signal ........................................................................................................... A-18
A.11 MBIST interface ..................................................................................................... A-19
A.12 Scan test signal ..................................................................................................... A-20
A.13 External Debug interface ....................................................................................... A-21
A.14 PTM interface signals ............................................................................................ A-24
Appendix B Cycle Timings and Interlock Behavior
B.1 About instruction cycle timing .................................................................................. B-2
B.2 Data-processing instructions ................................................................................... B-3
B.3 Load and store instructions ...................................................................................... B-4
B.4 Multiplication instructions ......................................................................................... B-7
B.5 Branch instructions .................................................................................................. B-8
B.6 Serializing instructions ............................................................................................. B-9
Appendix C Revisions

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design