EasyManuals Logo

ARM Cortex A9 User Manual

ARM Cortex A9
213 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #4 background imageLoading...
Page #4 background image
Contents
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. iv
ID073015 Non-Confidential
3.7 Modes of operation and execution ........................................................................... 3-8
3.8 Memory model ......................................................................................................... 3-9
3.9 Addresses in the Cortex-A9 processor ................................................................. 3-10
Chapter 4 System Control
4.1 About system control .............................................................................................. 4-2
4.2 Register summary .................................................................................................... 4-3
4.3 Register descriptions ............................................................................................. 4-18
Chapter 5 Jazelle DBX registers
5.1 About coprocessor CP14 ......................................................................................... 5-2
5.2 CP14 Jazelle register summary ............................................................................... 5-3
5.3 CP14 Jazelle register descriptions .......................................................................... 5-4
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................................ 6-2
6.2 TLB Organization ..................................................................................................... 6-4
6.3 Memory access sequence ....................................................................................... 6-6
6.4 MMU enabling or disabling ...................................................................................... 6-7
6.5 External aborts ......................................................................................................... 6-8
Chapter 7 Level 1 Memory System
7.1 About the L1 memory system .................................................................................. 7-2
7.2 Security Extensions support .................................................................................... 7-4
7.3 About the L1 instruction side memory system ......................................................... 7-5
7.4 About the L1 data side memory system .................................................................. 7-8
7.5 About DSB ............................................................................................................. 7-10
7.6 Data prefetching .................................................................................................... 7-11
7.7 Parity error support ................................................................................................ 7-12
Chapter 8 Level 2 Memory Interface
8.1 About the Cortex-A9 L2 interface ............................................................................ 8-2
8.2 Optimized accesses to the L2 memory interface ..................................................... 8-7
8.3 STRT instructions .................................................................................................... 8-9
Chapter 9 Preload Engine
9.1 About the Preload Engine ........................................................................................ 9-2
9.2 PLE control register descriptions ............................................................................ 9-3
9.3 PLE operations ........................................................................................................ 9-4
Chapter 10 Debug
10.1 Debug Systems ..................................................................................................... 10-2
10.2 About the Cortex-A9 debug interface .................................................................... 10-3
10.3 Debug register features ......................................................................................... 10-4
10.4 Debug register summary ....................................................................................... 10-5
10.5 Debug register descriptions ................................................................................... 10-7
10.6 Debug management registers ............................................................................. 10-13
10.7 Debug events ....................................................................................................... 10-15
10.8 External debug interface ...................................................................................... 10-16
Chapter 11 Performance Monitoring Unit
11.1 About the Performance Monitoring Unit ................................................................. 11-2
11.2 PMU register summary .......................................................................................... 11-3
11.3 PMU management registers .................................................................................. 11-5
11.4 Performance monitoring events ............................................................................. 11-7
Appendix A Signal Descriptions
A.1 Clock signals ............................................................................................................ A-2

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM Cortex A9 and is the answer not in the manual?

ARM Cortex A9 Specifications

General IconGeneral
ArchitectureARMv7-A
Cores1-4
SIMD ExtensionsNEON
ISAARM
MicroarchitectureCortex-A9
Instruction Width32-bit
Data Width32-bit
MMUYes
Instruction SetARMv7-A
Clock SpeedUp to 2 GHz
L1 Cache32 KB Instruction, 32 KB Data (per core)
Process Technology40 nm, 28 nm
Floating Point UnitVFPv3
Pipeline Depth8 stages
Power ConsumptionLow power design

Related product manuals