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Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide
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Chapter 14 Overview of the Serial SPAs
Supported MIBs
run at 100 percent DS3 line rate when those low bandwidth channels are idle (that is, not
transmitting or receiving packets). This issue does not occur if those low bandwidth channels are
not idle.
• The maximum number of channels supported on the channelized SPAs are:
–
1023 channels per SPA—On a 2-Port and 4-Port Channelized T3 SPA or 1-Port Channelized
OC-3/STM-1 SPA.
–
2000 NxDS0 per SPA—On a 1-Port Channelized OC-12/STM-4 SPA.
• On a 2-Port and 4-Port Channelized T3 SPA or 1-Port Channelized OC-3/STM-1 SPA, the maximum
number of FIFO buffers is 4096. The FIFO buffers are shared among the interfaces; how they are
shared is determined by speed. If all the FIFO buffers have been assigned to existing interfaces, a
new interface cannot be created, and the “%Insufficient FIFOs to create channel group” error
message is seen.
To find the number of available FIFO buffers, use the show controller t3 command:
Router# show controller t3 1/0/0
T3 1/0/0 is up.
Hardware is SPA-4XCT3/DS0
IO FPGA version: 2.6, HDLC Framer version: 0
T3/T1 Framer(1) version: 2, T3/T1 Framer(2) version: 2
SUBRATE FPGA version: 1.4
HDLC controller available FIFO buffers 3112
FIFO allocation information is provided in Table 14-1.
Supported MIBs
The following MIBs are supported for the serial SPAs on the Cisco ASR 1000 Series Routers.
Serial SPAs
• CISCO-ENTITY-ALARM-MIB
Ta b l e 14-1 FIFO Allocation
Number of Time Slots Number of FIFO Buffers
1–6 DS0 4
7–8 DS0 6
9 DS0 6
10–12 DS0 8
13–23 DS0 12
1–6 E1 TS 4
7–9 E1 TS 6
11–16 E1 TS 8
17–31 E1 TS 16
T1 12
E1 16
DS3 336