Cisco ASR 1000

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Cisco ASR 1000 Series Aggregation Services Routers SIP and SPA Software Configuration Guide
OL-14127-08
Chapter 6 Overview of the ATM SPAs
Displaying the SPA Hardware Type
3. The SAR engine receives the cells from the framer and reassembles the cells into the original
packets, temporarily storing them in a per-port receive buffer until they can be forwarded (using one
channel per physical port) to the field-programmable gate array (FPGA). The SAR engine discards
any cells that have been corrupted in transit.
Note Although the SAR in SPA Hardware has two channels to send EBFC and WRED statistics packets to
FPGA, the ASR does not enable WRED on SPA. Hence, WRED statistics packets are not sent by SAR
to FPGA, but EBFC statistics packets are sent by SAR to FPGA.
4. The FPGA receives the packets from the SAR engine and forwards them to the host processor (using
one channel per physical port) for further routing, switching, or additional processing. The FPGA
also collects the traffic statistics for the packets that it passes.
Path of Packets in the Egress Direction
The following steps describe the path of an egress packet as the SPA receives it from the router through
the SIP and converts it to ATM cells for transmission on the ATM network:
1. The FPGA receives the packets from the host processor (using one channel per physical port) and
stores them in its packet buffers until the SAR engine is ready to receive them. The ATM shim
header is replaced by the appropriate canonical header for the SAR and the whole packet is
forwarded to the SAR.
The FPGA also collects the traffic statistics for the packets that it passes, and any errored packets
are flagged and forwarded to the SAR. The FPGA uses two channels to forward traffic to the SAR:
one for AAL5 traffic and one for cell unbundling traffic.
2. The SAR engine receives the packets from the FPGA. If any errored data is detected, it is dropped
within the SAR. The SAR controls all of the traffic shaping and will drop traffic as necessary due to
congestion. The ATM cells are transmitted to the SONET/SDH framer using one channel per
physical port.
Note The SPA based L3 QoS features such as WRED and CBWFQ are not enabled for ATM SPAs on Cisco
ASR 1000 series routers. The WRED and CBWFQ features are done in the QFP (central processing
engine in ESP) as the QFP is more capable of handling these features on Cisco ASR 1000 series routers.
3. The SONET/SDH framer receives the cells from the SAR engine, optionally adds a header check
sequence (HCS) and scrambles the cell, and then inserts each cell into the SONET payload, adding
the necessary clocking, SONET overhead, and alarm information. The framer also inserts idle cells
as needed to fill the payload. The framer then transmits the payload along with the SONET frame
complete with all the appropriate section, line and path overhead.
4. The optical port conveys the optical data onto the physical layer of the ATM network.
Displaying the SPA Hardware Type
To verify the SPA hardware type that is installed in your Cisco ASR 1000 Series Routers, use the show
interfaces, or show controllers commands. A number of other show commands also provide
information about the SPA hardware.