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Intel 740 User Manual
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A
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B
B
C
C
D
D
PCI CONNECTORS
KEY
1 AND 2
KEY
3 DEVICE AGP
1.0
PCI CONNECTORS 1 & 2
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-79
FOLSOM, CA 95630
Custom
16
4
1
22:16:57
Title
Size
Document Number
Rev
Date:
Sheet
of
SDONEP1
AD29
AD8
AD3
AD25
AD26
SBOP1
AD14
C/BE#3
AD5
PU1_REQ64#
SERR#
PRSNT#22
C/BE#2
AD31
AD5
PRSNT#11
PERR#
PCIRST#
PIRQ#D
AD10
AD1
AD27
PIRQ#B
PRSNT#12
C/BE#2
C/BE#1
AD7
R_AD27
AD28
AD30
AD3
PU2_REQ64#
PRSNT#21
PAR
A_D25
AD13
AD9
PRSNT#11
PU1_REQ64#
PRSNT#22
PLOCK#
DEVSEL#
AD1
5
AD15
C/BE#3
PU2_ACK64
#
PU2_REQ64#
R_AD27
PIRQ#C
C/BE#0
AD12
AD24
AD23
PRSNT#12
PTRS
T#
AD7
AD21
AD23
AD16
AD18
AD13
IRDY#
AD0
AD11
C/BE#1
TRDY#
SBOP2
AD24
AD4
AD17
PU1_ACK64#
AD21
AD6
AD19
AD27
AD0
AD26
PU1_ACK64#
PCI_PME#
PTMS
AD14
AD22
C/BE#0
AD2
AD11
R_AD26
STOP#
PIRQ#A
PTC
K
AD29
AD9
AD26
AD22
AD18
FRAME#
PRSNT#21
PCI_PME#
AD10
AD17
AD28
AD4
AD20
AD12
AD19
AD20
AD2
PTDI
SDONEP2
AD1
AD8
AD16
R_AD26
AD31
AD6
AD30
PU2_ACK64#
AD27
SBOP1
SBOP2
SDONEP1
SDONEP2
VCC
VCC
VCC
+12V
VCC
VCC
VCC
-12V
VCC3
VCC3
VCC
VCC3
VCC3
VCC
-12V
+12V
C78
0.1 uF
R27
5.6K
C75
0.1 uF
RP48
5.6K
1
8
2
7
3
6
4
5
R30
5.6K
R62
100
J14
PCI_CONN
B7
B1
B8
A1
B2
B3
A2
B4
B5
A3
B6
A4
B9
A5
B10
B11
A6
B12
B13
A7
B14
B15
A8
B16
B17
A9
B18
B19
A10
B20
B21
A11
B22
B24
A12
B25
B26
A13
B27
B28
A14
B29
B30
A15
B31
B32
A16
B33
B34
A17
B35
B36
A18
B37
B38
A19
B39
B40
A20
B41
B23
B42
A21
B43
B44
A22
B45
B46
A23
B47
B48
A24
B49
B53
A25
B54
B55
A26
B56
B57
A27
B58
B52
B59
A28
B60
B61
A29
B62
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A53
A54
A55
A56
A57
A52
A58
A60
A61
A59
A62
INTB#
-12V
INTD#
TRST#
TCK
GND
+12V
TDO
+5V
TMS
+5V
TDI
PRSNT1#
+5V
RSV
PRSNT2#
INTA#
GND
GND
INTC#
RSV
GND
+5V
CLK
GND
RSV
REQ#
+5V
+5V
AD(31)
AD(29)
RSV
GND
AD(25)
GND
+3.3V
C/BE#3)
GND
AD(23)
GND
RSV
AD(21)
AD(19)
RESET#
+3.3V
AD(17)
+5V
C/BE#(2)
GND
GNT#
IRDY#
+3.3V
GND
DEVSEL#
GND
PME#
LOCK#
PERR#
AD(30)
+3.3V
AD(27)
SERR#
+3.3V
+3.3V
C/BE#(1)
AD(28)
AD(14)
GND
AD(26)
AD(12)
AD(10)
GND
GND
AD(7)
AD(24)
+3.3V
AD(5)
IDSEL
AD(3)
GND
+3.3V
AD(1)
AD(8)
+5V
AD(22)
ACK64#
+5V
AD(20)
+5V
GND
AD(18)
AD(16)
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD(15)
+3.3V
AD(13)
AD(11)
GND
AD(09)
+3.3V
AD(06)
AD(04)
GND
AD(02)
C/BE#(0)
AD(00)
REQ64#
+5V
+5V
+5V
R29
5.6K
R28
5.6K
R66
100
C77
0.1 uF
J13
PCI_CONN
B7
B1
B8
A1
B2
B3
A2
B4
B5
A3
B6
A4
B9
A5
B10
B11
A6
B12
B13
A7
B14
B15
A8
B16
B17
A9
B18
B19
A10
B20
B21
A11
B22
B24
A12
B25
B26
A13
B27
B28
A14
B29
B30
A15
B31
B32
A16
B33
B34
A17
B35
B36
A18
B37
B38
A19
B39
B40
A20
B41
B23
B42
A21
B43
B44
A22
B45
B46
A23
B47
B48
A24
B49
B53
A25
B54
B55
A26
B56
B57
A27
B58
B52
B59
A28
B60
B61
A29
B62
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A53
A54
A55
A56
A57
A52
A58
A60
A61
A59
A62
INTB#
-12V
INTD#
TRST#
TCK
GND
+12V
TDO
+5V
TMS
+5V
TDI
PRSNT1#
+5V
RSV
PRSNT2#
INTA#
GND
GND
INTC#
RSV
GND
+5V
CLK
GND
RSV
REQ#
+5V
+5V
AD(31)
AD(29)
RSV
GND
AD(25)
GND
+3.3V
C/BE#3)
GND
AD(23)
GND
RSV
AD(21)
AD(19)
RESET#
+3.3V
AD(17)
+5V
C/BE#(2)
GND
GNT#
IRDY#
+3.3V
GND
DEVSEL#
GND
PME#
LOCK#
PERR#
AD(30)
+3.3V
AD(27)
SERR#
+3.3V
+3.3V
C/BE#(1)
AD(28)
AD(14)
GND
AD(26)
AD(12)
AD(10)
GND
GND
AD(7)
AD(24)
+3.3V
AD(5)
IDSEL
AD(3)
GND
+3.3V
AD(1)
AD(8)
+5V
AD(22)
ACK64#
+5V
AD(20)
+5V
GND
AD(18)
AD(16)
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD(15)
+3.3V
AD(13)
AD(11)
GND
AD(09)
+3.3V
AD(06)
AD(04)
GND
AD(02)
C/BE#(0)
AD(00)
REQ64#
+5V
+5V
+5V
C76
0.1 uF
RP68B
2.7K
2
7
RP68A
2.7K
1
8
RP68C
2.7K
3
6
RP68D
2.7K
4
5
STOP
#
7,12,17,28
TRDY
#
7,12,17,28
PGNT#
0
7,28
AD[31:0
]
7,12,17
PTD
I
17
PERR
#
17,28
PGNT#
1
7,28
PCIRST
#
6,12,15,17,38
PCLK
1
5
PTC
K
17
PREQ#
0
7,28
IRDY
#
7,12,17,28
C/BE#[3:0
]
7,12,17
PIRQ#
B
13,15,17,28
PA
R
7,12,17,28
PIRQ#
D
13,17,28
PCI_PME
#
13,28
PIRQ#
A
13,15,17,28,34
PLOCK
#
7,17,28
SERR
#
7,12,17,28
PREQ#
1
7,28
PTRS
T
#
17
FRAME
#
7,12,17,28
PCLK
2
5
PIRQ#
C
13,17,28
DEVSEL
#
7,12,17,28
PTM
S
17
101
103
Table of Contents
Table of Contents
3
Revision History
8
Introduction
9
About this Design Guide
11
References
12
Addin Card Design
15
Introduction
15
Design Features
16
Intel740™ Graphics Accelerator
16
MIX and Match Options for Intel740™ Graphics Accelerator Card
16
BT829B - Video Decoder
17
BT869 - TV Encoder
17
Terminology
17
Power Sources
17
Intel740™ Graphics Accelerator Power Supplies
17
Fences
18
Stitching
18
Example of Power Plane Separation ("Fencing")
18
Example of Power Plane Stitching
18
Major Signal Sections
19
Board Description
20
Layout and Routing Guidelines
19
Placement
19
Example ATX Layout
20
Four Layer Board Stack-Up
21
BGA Component
22
Layout Requirements
22
Metal Defined Land Dimensions
22
BGA Trace
22
Ground Connections
23
Power Connections
23
Dogbone Via Pattern
23
Decoupling
24
Suggested VCC Planes for the Intel740™ Graphics Accelerator
24
Intel740™ Graphics Accelerator Decoupling
24
General Signal Routing
25
Voltage Regulator
25
Bt829 Video Decoder
25
Intel740™ Graphics Accelerator BGA Routing Example
25
Ground Planes
26
Power Planes
26
Passive Components and Signal Routing
26
Bt869 Video Encoder
26
Bt829B GND and AGND Pins
26
Bt829B VCC and AVCC Pins
26
Power Planes
27
Passive Components and Signal Routing
27
AGP Layout and Routing Guidelines
27
Bt869 Digital and Analog Power Pins
27
AGP Signal Lengths
27
Strobes and Corresponding Signal Groups
27
Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines
28
Supported Memory Options
28
Memory Layout Restrictions (See Figure 2-12 and Figure 2-13)
28
Memory Layout Restrictions (See Figure 2-14 and Figure 2-15)
29
Layout Dimensions (MA[11:0])
29
Layout Dimensions (MD[63:0], DQM[7:0])
29
Layout Dimensions (WEA#, SRASA#, SCASA#, CSA1#, CSB0#)
29
Memory Layout Restrictions (See Figure 2-16 and Figure 2-17)
30
Intel740™ Graphics Accelerator Memory Configurations
31
Layout Dimensions (WEB#, SRASB#, SCASB#, CSA0#)
30
Memory Layout Dimensions (TCLK0)
30
Memory Layout Dimensions (TCLK1)
30
Memory Layout Dimensions (RCLK and OCLK to RCLK)
31
MB Local Memory Connection (64-Bit Data Path)
31
TV out Interface
34
Analog Signals
34
UL and FCC Considerations
34
TV Out/Roma Trace Lengths (See Figure 2-22)
34
Layout Dimensions, Digital TV Bus
34
GPIO Functions
35
Addin Card Schematics
35
512Kx32 and 256Kx32 Pinout Compatibility
38
Device AGP Motherboard Design
59
Introduction
59
Overview
59
About this Chapter
60
Block Diagram
60
Implementation Issues
61
Disabling a Master Device
61
Low Power Logic Implementation
62
State of Signals to be Driven after System Reset but at Least One Clock Prior to Asserting TEST
62
GPO27# and GPO28# Signal Duration
63
The Schematic Diagram for GPO27#, PCIRST# (System Reset), RESET#, ROMA16 Signals
62
Signal Duration of the GPO Signals from PIIX4
63
State Diagrams
64
The Schematic Diagram for the WEB#, SCASB#, SRASB#, CS0B#, CS1B# and TEST
63
Intel740™ Graphics Controller (on Board Device) Remains in Low Power Mode
64
Intel740™ Graphics Controller (on Board Device) State Diagram
64
Signal Quality and Timing Issues
65
Strobe Edge Quality Issues
65
Clock Issues
66
Point-To-Point Topology
66
Design Recommendations
67
General Design Recommendation
67
Voltage Definitions
67
Device AGP Motherboard Layout and Routing Guidelines
67
BGA Quadrant Assignment
68
Major Signal Sections
68
Example ATX Placement for a up Pentium
69
Intel ® 440BX Agpset / Intel 740 Graphics Accelerator Design
69
Board Description
70
3-Point AGP Design Guidelines
70
Layout and Routing
70
Four Layer Board Stack-Up
70
Data and Strobe Definitions
71
Data and Associated Strobe
71
Assumptions for Board Design Guidelines
72
Add-In Card Guideline Assumptions
72
Motherboard Guideline Assumptions
72
Data Signal and Strobe Guideline Assumptions
72
Control and Clock Signal Guideline Assumptions
72
Data Signal and Strobe Requirements
72
Control Signal Line Length Requirements
73
3-Load AGP Topology
74
Overall Solution Space
74
Point-To-Point Topology
73
Strobe and Data Segment Solution Space
74
Device Data Load Topology
74
Device Strobe Load Topology
74
Device Data Load Topology (Solution 1 Is Shown)
75
Device Strobe Load Topology (Solution 1 Is Shown)
75
Clock Topology and Matching
75
Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines
76
Clock Segment Solution Space
76
Supported Memory Options
76
Memory Layout Restrictions (See Figure 3-16 and Figure 3-17)
77
Memory Layout Restrictions (See Table 3-16 and Table 3-17)
77
Layout Dimensions (MA[11:0])
77
Layout Dimensions (MD[63:0], DQM[7:0])
77
Memory Layout Restrictions (See Figure 3-19)
78
Device AGP Intel740™ Graphics Accelerator Memory Configurations
79
Layout Dimensions (WEA#, SRASA#, SCASA#, CSA0#)
78
Memory Layout Dimensions (TCLK1)
78
Memory Layout Dimensions (RCLK and OCLK to RCLK)
79
Pentium
80
Device AGP Motherboard Reference Design Schematics
80
512Kx32 and 256Kx32 Pinout Compatibility
84
DIMM Socket
95
Usb Connectors
106
Thermal Considerations
128
Thermal Design Considerations Chart
130
Mechanical Information
132
Mounting Hole Locations (Fan/Heatsink Assembly)
134
Board Dimensions
134
Fan/Heatsink Hole Pattern
134
DVD Daughter Card Dimensions (ATX and NLX)-Top Side
135
VMI Header Placement
135
Pin Video Connector Schematic
136
Pin Video Connector
136
Recommended Bracket Placement
137
Recommended Bracket Cutout
137
Bracket
137
NLX Considerations
138
Third Party Vendors
140
Voltage Regulator
142
50 Pin Connector
142
Fan/Heatsink
142
Flash Components
142
Video Encoders/Decoders
142
DVD Daughter Cards
143
TV Tuner
143
Application Note 653: Thermal Design Considerations
146
Table of Contents
147
Document Goals
149
Importance of Thermal Management
149
Introduction
149
Intel740™ Graphics Accelerator Packaging Terminology
150
Case Temperature
151
Thermal Specifications
151
Power
152
Airflow Management
153
Designing for Thermal Performance
153
Cooling Solutions
155
System Fans
155
Fan Placement
155
Fan Direction
157
Size and Quantity
157
Fan Venting
157
Vent Placement
157
Vent Area/Size
157
Vent Shape
158
Ducting
158
Ducting Placement
158
Thermal Enhancements
158
Clearance
158
Low Profile Fan Heat Sink
159
Low Profile Fan Heat Sink PCB Layout Guidelines
159
Low Profile Fan Heat Sink Electrical Requirements
160
Low Profile Fan Heat Sink Attach
161
Low Profile Fan Heat Sink Reliability
161
Low Profile Passive Heat Sink
162
Clip Attach
162
Epoxy
162
Tape Attach
163
Reliability
165
Thermal Interface Management for Heat Sink Solutions
165
Bond Line Management
166
Interface Material Performance
166
Case Temperature Measurements
167
Measurements for Thermal Specifications
167
Power Simulation Software
168
Conclusion
170
Attach Sales Locations
171
Low Profile Fan Heat Sink Sales Locations
171
Low Profile Passive Heat Sink Sales Locations
171
Sources
171
Table of Contents
177
Contents
179
Introduction
179
Low Power Mode Overview
179
State Diagrams
180
Supported Single Monitor and Mulitmonitor Configurations
182
Figures
182
Software Sequence
182
Low Power Mode
182
Tables
182
Monitor and Mulitmonitor Configurations
182
Table of Contents
189
1 Introduction
191
Convention Used
191
Objective
191
Scope of this Document
191
2 Pinout
192
Pin Functional Descriptions (Simplified)
194
3 Control Registers
195
Mode Register and Modes Required to be Supported
195
Special Mode Register
195
Color Register
196
4 Command Truth Table
197
5 Operative Command Table
198
6 Row/Column Addressing Per Memory Size/# Banks
203
7 Functional Description
204
Initialization Sequence
204
Power up Sequence
204
NOP and Device Deselect
205
Precharge All
205
Precharge Selected Bank
205
Read Bank
205
Row Activate
205
Write Bank
205
Block Write
206
Mode Register Set
206
Power down Mode
207
8 Essential Functionality for the "PC SGRAM" Device
208
Burst Read and Burst Write
208
Multi- Bank Ping Pong Access
208
Precharge Command after a Burst Read
208
Read and Write with Autoprecharge
208
Precharge Command after a Burst Write
209
Precharge Termination of a Burst Read
209
Precharge Termination of a Burst Write
209
Read Terminated by Read
209
Read Terminated by Write
209
Write Terminated by Read
209
Write Terminated by Write
209
Auto Refresh (CBR) Command
210
Back to Back Command Support
210
9 SGRAM AC/DC Parameters
211
DC Specifications for 100-166 Mhz
211
Specifications for 100-166 Mhz
211
A.C. Timing Parameters for 100-166 Mhz
212
A.C. Specifications for 166-250 Mhz
213
A.C. Timing Parameters for 166-250 Mhz
213
DC Specifications for 166-250 Mhz
213
IBIS: I/V Characteristics for Input and Output Buffers
214
IBIS Reference
215
Table of Contents
219
General Features
221
Labeling
221
Unbuffered Graphics SO-DIMM Module
221
Mechanical Outline
222
Environmental Requirements
223
Pin Assignments
224
Graphics SO-DIMM Block Diagram
225
Address Translation
229
Configuration
229
Default Parameters
229
Clock Frequency and Memory Timing
231
Resistor Strapping Options
231
Serial Presence Detect EEPROM
231
15 Ns Timing
232
Electrical Characteristics
232
10 Ns Timing
233
Timing Diagrams
234
PCB Layout Considerations
236
Clock Routing and Chip Selects
237
Address/Control Routing
238
Data Routing
239
Electrical Specifications
241
Operating Requirements
241
Sdram/Sgram Components D.C. Operating Requirements
241
Memory Timing
242
5
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Intel 740 Specifications
General
Brand
Intel
Model
740
Category
Video Card
Language
English
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