iv
Revision 0.91
Figures
1 SDRAM SO-DIMM Module ..............................................................................2
2 256K/512 x 64 SGRAM SO-DIMM Block Diagram
(1 bank of two 256K/512K x 32) ......................................................................5
3 512K/1M x 64 SGRAM SO-DIMM Block Diagram
(2 banks of two 256K/512K x 32).....................................................................6
4 256K/512K x 32 SGRAM SO-DIMM Block Diagram
(1 bank of one 256K/512K x 32)......................................................................7
5 512K/1M x 32 SGRAM SO-DIMM Block Diagram
(2 banks of one 256K/512K x 32) ....................................................................8
6 Address/Control A.C. Timing Parameters......................................................14
7 Data Write A.C. Timing Parameters ..............................................................14
8 Data Read A.C. Timing Paramters ................................................................15
9 T-Topology Clock Routing .............................................................................17
10 Address and Control Routing.........................................................................18
11 Data Routing..................................................................................................19
12 Silk Screen - Primary Side.............................................................................23
13 Silk Screen - Secondary Side ........................................................................23
14 Primary Side (layer 1)....................................................................................24
15 VCC Plane (layer 2).......................................................................................24
16 Inner-Signal (layer 3) .....................................................................................25
17 Inner-Signal (layer 4) .....................................................................................25
18 Ground Plane (layer 5) ..................................................................................26
19 Secondary Side (layer 6) ...............................................................................26
Tables
1 Environmental Requirements ..........................................................................3
2 SO-DIMM Module Pin Assignments ................................................................4
3 Address Translation.........................................................................................9
4 Module Baseline Component Requirements .................................................10
5 Signal Loading...............................................................................................16
6 Stub Lengths (Clock and Chip Select Routing) .............................................17
7 Stub Lengths (Address/Control Routing) .......................................................18
8 Byte Ordering.................................................................................................19
9 Stub Lengths (Data Line Routing) .................................................................20
10 Absolute Maximum Ratings ...........................................................................21
11 D.C. Operating Requirements .......................................................................21
12 Absolute Maximum A.C. Operating Requirements ........................................21
To Next Page
Loading...
Need help?
General