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Intel 740 User Manual
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INTEL740 (A)
VENDOR ID IS 0X
8086
NOTE:
-----
THIS I.D. NEEDS
TO
REFLECT BOARD VEN
DOR
SUBSYSTEM ID IS 0
X100
1%
1%
1%
USE TANTALUM CAPACITORS FOR 10
AND 22UF
Intel740(TM) Graphics Accelerator Refere
nce Card
2.1
Intel740(TM) Graph
ics Accelerator(A)
C
3
16
Th
ursday, April 09, 1998
Title
Size
Document Number
Rev
Date:
Sheet
of
TP_03J26
SBA7
SBA1
ROMA7
ROMA2
TP_03L24
AD21
3VVP14
AD30
AD22
AD12
ROMA13
ROMA5
3VVP2
ROMA0
SBA4
AD2
ROMA11
3VROMD4
3VROMD2
3VROMD0
AD26
AD17
AD6
ROMA14
ROMA9
3VVP3
AD31
AD5
AD3
3VVP7
3VVP4
3VVP0
3VROMD1
ST1
SBA6
AD23
AD4
IREFSET#
SBA0
AD28
AD13
3VVP11
ROMA15
AD1
ROMA8
ROMA1
ST0
AD27
AD25
AD19
ROMA10
ROMA6
VMIHA3
AD20
AD8
ROMA16
SBA5
SBA3
3VVP12
ROMA4
ROMA3
VMIHA0
AD9
AD7
3VVP9
3VVP5
VMIHA4
VMIHA2
TP_03L23
3VVP15
AD10
AD15
3VVP8
AD14
ST2
AGPREF
3VROMD5
AD29
ROMA17
3VROMD3
AD24
AD18
3VVP10
ROMA12
VMIHA1
SBA2
AD11
3VVP13
AD16
3VVP6
AD0
3VROMD7
3VROMD6
3VVP1
VCC3
VCC3
VDDQ
VCC_CORE
VCC3
VDDQ
VCC3
VCC3
VDDQ
VDDQ
VCC3
VCC3
R22
2K
R47
2K
R52
2K
R51
2K
R55
2K
C127
.01UF
R60
182
R59
267
R24
562
AGP INTERFACE
VIDEO CAPTURE
BIOS INTERFACE
U9A
INTEL740
VCC
E07
VP15
B21
VCC
F25
VCC
E09
VSS
AE23
VRDY#
J24
VCCA
G23
VCC
E11
VSS
AE24
VCCP
G25
VCC
E13
HREF#
K22
VCC
E14
VSS
AE25
VCC
E16
VCCA
G26
VCC
E18
VREF#
L23
VCC
E20
VSS
AE26
VCC
H22
VCLK
L24
VCC
AB07
VSS
AF01
VCC
AB09
VSS
AF02
VCC
AB11
VSS
AF03
VCC
AB13
VSS
F06
VCC
AB14
VSS
F07
VCC
AB18
VSS
F20
VCC
AB16
VCC
AB20
VSS
F21
VSS
F22
VSSA
F23
VSS
G06
VSS
G21
VSSA
H24
VSS
AF04
VSS
AF05
VSS
AF22
VSS
A01
VCCP
D06
VSS
A02
VCCP
AC06
VSS
A03
VCCP
E08
VDDQ
GO5
VSS
B05
VSS
B22
VSS
B23
VSS
B24
VSS
B25
VSS
B26
VSS
C01
VSS
C02
VSS
C03
VSS
C04
VSS
C05
VSS
C22
VSS
C23
VSS
C24
VSS
C25
VSS
C26
VSS
D01
VSS
D02
VSS
D03
VSS
D04
VSS
D05
VSS
D22
VSS
D23
VSS
D24
VSS
D25
VSS
D26
VSS
E01
VSS
E02
VSS
E03
VSS
E04
VSS
E05
VSS
E06
VSS
E21
VSS
E22
VSS
E23
VSS
E24
VSS
E25
VSS
E26
VSSA
F03
VSS
F05
VCCP
E10
VCCP
AB08
VCCP
E12
VCCP
D13
VCCP
AB10
VCCP
D14
VDDQ
J05
VCCP
E15
VCCP
AB12
VCCP
E17
VCCP
E19
VCCP
AC13
VDDQ
L05
VCCP
AC14
VCCP
AB15
VDDQ
N05
VCCP
AB17
NC
H26
VCCP
AB19
VDDQ
P05
VCCP
AC21
VCCP
Y22
VDDQ
T05
VCCP
V22
VCCP
T22
VDDQ
V05
VCCP
P22
VCCP
N22
VDDQ
Y05
VCCP
L22
VCCP
J22
VCCP
G22
NC
H25
VSS
A04
VSS
A05
VSS
A22
VSS
A23
VSS
A24
VSS
A26
VSS
B01
VSS
B02
VSS
B04
VSS
A25
VSS
B03
ST0
G01
VMIHA0
A16
ST1
H04
ROMD0
B07
ST2
H03
VMIHA1
D15
ROMA0
A07
VMIHA2
C15
ROMD1
A06
VMIHA3
B15
VP0
C17
VMIHA4
A15
ROMD2
B06
ROMA1
B08
ROMD3
C06
C/BE0#
V04
ROMD4
D07
ROMA2
A08
ROMD5
C07
VP1
A18
ROMD6
D08
ROMA3
B09
ROMD7
C08
AD0
Y04
ROMOE#
C09
ROMA4
A09
ROMWE#
C13
VP2
D17
ROMA5
B10
C/BE1#
U01
ROMA6
A10
VP3
B18
ROMA7
B11
AD14
U02
ROMA8
D11
VP4
C18
ROMA9
C10
C/BE2#
R01
ROMA10
D09
VP5
A19
ROMA11
D10
AD1
Y02
ROMA12
A11
VP6
D18
ROMA13
C11
C/BE3#
M03
ROMA14
D12
VP7
B19
ROMA15
B12
AD2
Y03
ROMA16
A12
VP8
C19
ROMA17
C12
AD15
T04
VP9
A20
AD3
Y01
VP10
D19
AD4
W05
VP11
B20
AD16
P03
VP12
C20
AD5
W03
VP13
A21
AD6
W04
VP14
D20
AD17
P02
AD7
W02
AD8
V02
AD18
P04
AD9
V03
AD10
V01
AD19
P01
AD11
U05
AD12
U03
AD20
N03
AD13
U04
AD21
N01
AD22
N04
AD23
N02
AD24
M04
AD25
M02
AD26
M05
AD27
L01
AD28
L03
AD29
L02
AD30
L04
AD31
K01
CLK
F02
SBA0
H01
SBA1
J04
SBA2
J02
SBA3
J03
SBA4
K03
SBA5
K05
SBA6
K02
SBA7
K04
RESET#
G03
INT
G04
STOP#
R05
PAR
T03
TRDY#
R04
IRDY#
T01
FRAME#
R03
DEVSEL
T02
REQ#
G02
GNT
H05
IREFSET#
D21
VSS
L25
VSSA
AA02
VMIINT#
B17
VMIRDY
A17
VMIRD#
D16
VMIWR#
C16
VMICS#
B16
DBF#
H02
SBSTB
J01
ADSTB_0
W01
ADSTB_1
M01
AGPREF
R02
LEFT
J23
VSS
L11
VSS
L12
C117
.1UF
C123
.1UF
C98
.01UF
C133
.01UF
C121
10UF
C132
.1UF
C44
.01UF
C112
.1UF
C131
.1UF
C130
.1UF
C110
.1UF
C17
22UF
C70
.01UF
C113
.1UF
C126
.1UF
C39
10UF
C111
.1UF
C128
.1UF
C116
.01UF
C114
.01UF
C124
.1UF
C125
.1UF
C54
.1UF
C76
.01UF
C109
.01UF
C115
.01UF
C74
.1UF
3VVP[15:0]
6,11
3VROMD[7:0]
15
ROMA[17:0]
7,15
VMIHA[4:0]
8
AD[31:0]
9
ST[2:0]
9
SBA[7:0]
9
3VVMIRDY
11
3VVREF
6,11
3VVMIINT#
11
FRAME#
9
3VVCLK
6,11
PAR
9
3VVRDY
11
VMIWR#
8
ROMWE#
15
GNT#
9
AD_STB_A
9
VMIRD#
8
AD_STB_B
9
VMICS#
8
DEVSEL#
9
STOP#
9
CLK
9
CBE3#
9
CBE1#
9
ROMOE#
15
CBE0#
9
IRDY#
9
INTA#
9
RESET#
6,7,8,9
TRDY#
9
CBE2#
9
3VHREF
6,11
SB_STB
9
DBF#
9
REQ#
9
42
44
Table of Contents
Table of Contents
3
Revision History
8
Introduction
9
About this Design Guide
11
References
12
Addin Card Design
15
Introduction
15
Design Features
16
Intel740™ Graphics Accelerator
16
MIX and Match Options for Intel740™ Graphics Accelerator Card
16
BT829B - Video Decoder
17
BT869 - TV Encoder
17
Terminology
17
Power Sources
17
Intel740™ Graphics Accelerator Power Supplies
17
Fences
18
Stitching
18
Example of Power Plane Separation ("Fencing")
18
Example of Power Plane Stitching
18
Major Signal Sections
19
Board Description
20
Layout and Routing Guidelines
19
Placement
19
Example ATX Layout
20
Four Layer Board Stack-Up
21
BGA Component
22
Layout Requirements
22
Metal Defined Land Dimensions
22
BGA Trace
22
Ground Connections
23
Power Connections
23
Dogbone Via Pattern
23
Decoupling
24
Suggested VCC Planes for the Intel740™ Graphics Accelerator
24
Intel740™ Graphics Accelerator Decoupling
24
General Signal Routing
25
Voltage Regulator
25
Bt829 Video Decoder
25
Intel740™ Graphics Accelerator BGA Routing Example
25
Ground Planes
26
Power Planes
26
Passive Components and Signal Routing
26
Bt869 Video Encoder
26
Bt829B GND and AGND Pins
26
Bt829B VCC and AVCC Pins
26
Power Planes
27
Passive Components and Signal Routing
27
AGP Layout and Routing Guidelines
27
Bt869 Digital and Analog Power Pins
27
AGP Signal Lengths
27
Strobes and Corresponding Signal Groups
27
Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines
28
Supported Memory Options
28
Memory Layout Restrictions (See Figure 2-12 and Figure 2-13)
28
Memory Layout Restrictions (See Figure 2-14 and Figure 2-15)
29
Layout Dimensions (MA[11:0])
29
Layout Dimensions (MD[63:0], DQM[7:0])
29
Layout Dimensions (WEA#, SRASA#, SCASA#, CSA1#, CSB0#)
29
Memory Layout Restrictions (See Figure 2-16 and Figure 2-17)
30
Intel740™ Graphics Accelerator Memory Configurations
31
Layout Dimensions (WEB#, SRASB#, SCASB#, CSA0#)
30
Memory Layout Dimensions (TCLK0)
30
Memory Layout Dimensions (TCLK1)
30
Memory Layout Dimensions (RCLK and OCLK to RCLK)
31
MB Local Memory Connection (64-Bit Data Path)
31
TV out Interface
34
Analog Signals
34
UL and FCC Considerations
34
TV Out/Roma Trace Lengths (See Figure 2-22)
34
Layout Dimensions, Digital TV Bus
34
GPIO Functions
35
Addin Card Schematics
35
512Kx32 and 256Kx32 Pinout Compatibility
38
Device AGP Motherboard Design
59
Introduction
59
Overview
59
About this Chapter
60
Block Diagram
60
Implementation Issues
61
Disabling a Master Device
61
Low Power Logic Implementation
62
State of Signals to be Driven after System Reset but at Least One Clock Prior to Asserting TEST
62
GPO27# and GPO28# Signal Duration
63
The Schematic Diagram for GPO27#, PCIRST# (System Reset), RESET#, ROMA16 Signals
62
Signal Duration of the GPO Signals from PIIX4
63
State Diagrams
64
The Schematic Diagram for the WEB#, SCASB#, SRASB#, CS0B#, CS1B# and TEST
63
Intel740™ Graphics Controller (on Board Device) Remains in Low Power Mode
64
Intel740™ Graphics Controller (on Board Device) State Diagram
64
Signal Quality and Timing Issues
65
Strobe Edge Quality Issues
65
Clock Issues
66
Point-To-Point Topology
66
Design Recommendations
67
General Design Recommendation
67
Voltage Definitions
67
Device AGP Motherboard Layout and Routing Guidelines
67
BGA Quadrant Assignment
68
Major Signal Sections
68
Example ATX Placement for a up Pentium
69
Intel ® 440BX Agpset / Intel 740 Graphics Accelerator Design
69
Board Description
70
3-Point AGP Design Guidelines
70
Layout and Routing
70
Four Layer Board Stack-Up
70
Data and Strobe Definitions
71
Data and Associated Strobe
71
Assumptions for Board Design Guidelines
72
Add-In Card Guideline Assumptions
72
Motherboard Guideline Assumptions
72
Data Signal and Strobe Guideline Assumptions
72
Control and Clock Signal Guideline Assumptions
72
Data Signal and Strobe Requirements
72
Control Signal Line Length Requirements
73
3-Load AGP Topology
74
Overall Solution Space
74
Point-To-Point Topology
73
Strobe and Data Segment Solution Space
74
Device Data Load Topology
74
Device Strobe Load Topology
74
Device Data Load Topology (Solution 1 Is Shown)
75
Device Strobe Load Topology (Solution 1 Is Shown)
75
Clock Topology and Matching
75
Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines
76
Clock Segment Solution Space
76
Supported Memory Options
76
Memory Layout Restrictions (See Figure 3-16 and Figure 3-17)
77
Memory Layout Restrictions (See Table 3-16 and Table 3-17)
77
Layout Dimensions (MA[11:0])
77
Layout Dimensions (MD[63:0], DQM[7:0])
77
Memory Layout Restrictions (See Figure 3-19)
78
Device AGP Intel740™ Graphics Accelerator Memory Configurations
79
Layout Dimensions (WEA#, SRASA#, SCASA#, CSA0#)
78
Memory Layout Dimensions (TCLK1)
78
Memory Layout Dimensions (RCLK and OCLK to RCLK)
79
Pentium
80
Device AGP Motherboard Reference Design Schematics
80
512Kx32 and 256Kx32 Pinout Compatibility
84
DIMM Socket
95
Usb Connectors
106
Thermal Considerations
128
Thermal Design Considerations Chart
130
Mechanical Information
132
Mounting Hole Locations (Fan/Heatsink Assembly)
134
Board Dimensions
134
Fan/Heatsink Hole Pattern
134
DVD Daughter Card Dimensions (ATX and NLX)-Top Side
135
VMI Header Placement
135
Pin Video Connector Schematic
136
Pin Video Connector
136
Recommended Bracket Placement
137
Recommended Bracket Cutout
137
Bracket
137
NLX Considerations
138
Third Party Vendors
140
Voltage Regulator
142
50 Pin Connector
142
Fan/Heatsink
142
Flash Components
142
Video Encoders/Decoders
142
DVD Daughter Cards
143
TV Tuner
143
Application Note 653: Thermal Design Considerations
146
Table of Contents
147
Document Goals
149
Importance of Thermal Management
149
Introduction
149
Intel740™ Graphics Accelerator Packaging Terminology
150
Case Temperature
151
Thermal Specifications
151
Power
152
Airflow Management
153
Designing for Thermal Performance
153
Cooling Solutions
155
System Fans
155
Fan Placement
155
Fan Direction
157
Size and Quantity
157
Fan Venting
157
Vent Placement
157
Vent Area/Size
157
Vent Shape
158
Ducting
158
Ducting Placement
158
Thermal Enhancements
158
Clearance
158
Low Profile Fan Heat Sink
159
Low Profile Fan Heat Sink PCB Layout Guidelines
159
Low Profile Fan Heat Sink Electrical Requirements
160
Low Profile Fan Heat Sink Attach
161
Low Profile Fan Heat Sink Reliability
161
Low Profile Passive Heat Sink
162
Clip Attach
162
Epoxy
162
Tape Attach
163
Reliability
165
Thermal Interface Management for Heat Sink Solutions
165
Bond Line Management
166
Interface Material Performance
166
Case Temperature Measurements
167
Measurements for Thermal Specifications
167
Power Simulation Software
168
Conclusion
170
Attach Sales Locations
171
Low Profile Fan Heat Sink Sales Locations
171
Low Profile Passive Heat Sink Sales Locations
171
Sources
171
Table of Contents
177
Contents
179
Introduction
179
Low Power Mode Overview
179
State Diagrams
180
Supported Single Monitor and Mulitmonitor Configurations
182
Figures
182
Software Sequence
182
Low Power Mode
182
Tables
182
Monitor and Mulitmonitor Configurations
182
Table of Contents
189
1 Introduction
191
Convention Used
191
Objective
191
Scope of this Document
191
2 Pinout
192
Pin Functional Descriptions (Simplified)
194
3 Control Registers
195
Mode Register and Modes Required to be Supported
195
Special Mode Register
195
Color Register
196
4 Command Truth Table
197
5 Operative Command Table
198
6 Row/Column Addressing Per Memory Size/# Banks
203
7 Functional Description
204
Initialization Sequence
204
Power up Sequence
204
NOP and Device Deselect
205
Precharge All
205
Precharge Selected Bank
205
Read Bank
205
Row Activate
205
Write Bank
205
Block Write
206
Mode Register Set
206
Power down Mode
207
8 Essential Functionality for the "PC SGRAM" Device
208
Burst Read and Burst Write
208
Multi- Bank Ping Pong Access
208
Precharge Command after a Burst Read
208
Read and Write with Autoprecharge
208
Precharge Command after a Burst Write
209
Precharge Termination of a Burst Read
209
Precharge Termination of a Burst Write
209
Read Terminated by Read
209
Read Terminated by Write
209
Write Terminated by Read
209
Write Terminated by Write
209
Auto Refresh (CBR) Command
210
Back to Back Command Support
210
9 SGRAM AC/DC Parameters
211
DC Specifications for 100-166 Mhz
211
Specifications for 100-166 Mhz
211
A.C. Timing Parameters for 100-166 Mhz
212
A.C. Specifications for 166-250 Mhz
213
A.C. Timing Parameters for 166-250 Mhz
213
DC Specifications for 166-250 Mhz
213
IBIS: I/V Characteristics for Input and Output Buffers
214
IBIS Reference
215
Table of Contents
219
General Features
221
Labeling
221
Unbuffered Graphics SO-DIMM Module
221
Mechanical Outline
222
Environmental Requirements
223
Pin Assignments
224
Graphics SO-DIMM Block Diagram
225
Address Translation
229
Configuration
229
Default Parameters
229
Clock Frequency and Memory Timing
231
Resistor Strapping Options
231
Serial Presence Detect EEPROM
231
15 Ns Timing
232
Electrical Characteristics
232
10 Ns Timing
233
Timing Diagrams
234
PCB Layout Considerations
236
Clock Routing and Chip Selects
237
Address/Control Routing
238
Data Routing
239
Electrical Specifications
241
Operating Requirements
241
Sdram/Sgram Components D.C. Operating Requirements
241
Memory Timing
242
5
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Intel 740 Specifications
General
Brand
Intel
Model
740
Category
Video Card
Language
English
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