Intel 740

Intel740™ Graphics Accelerator Design Guide v
Figures
2-1 Example of Power Plane Separation ("fencing")...........................................2-4
2-2 Example of Power Plane Stitching................................................................2-4
2-3 Major Signal Sections ...................................................................................2-5
2-4 Example ATX Layout ....................................................................................2-6
2-5 Four Layer Board Stack-up...........................................................................2-7
2-6 Metal Defined land dimensions.....................................................................2-8
2-7 BGA Trace ....................................................................................................2-8
2-8 Dogbone Via Pattern.....................................................................................2-9
2-9 Suggested VCC Planes for the Intel740™ Graphics Accelerator...............2-10
2-10 Intel740™ Graphics Accelerator Decoupling..............................................2-10
2-11 Intel740™ Graphics Accelerator BGA Routing Example............................2-11
2-12 Layout Dimensions (MA[11:0])....................................................................2-15
2-13 Layout Dimensions (MD[63:0], DQM[7:0])..................................................2-15
2-14 Layout Dimensions (WEA#, SRASA#, SCASA#, CSA1#, CSB0#).............2-15
2-15 Layout Dimensions (WEB#, SRASB#, SCASB#, CSA0#)..........................2-16
2-16 Memory Layout Dimensions (TCLK0).........................................................2-16
2-17 Memory Layout Dimensions (TCLK1).........................................................2-16
2-18 Memory Layout Dimensions (RCLK and OCLK to RCLK)..........................2-17
2-19 2/4 MB Local Memory Connection (64-bit data path) .................................2-17
2-20 4/8 MB Local Memory Connection (64-bit data path) .................................2-18
2-21 8 MB Local Memory Connection (64-bit data path) ....................................2-19
2-22 Layout Dimensions, Digital TV Bus.............................................................2-20
2-23 512Kx32 and 256Kx32 Pinout Compatibility...............................................2-24
2-24 1M X 16 Pinout Compatibility.....................................................................2-24
3-1 Pentium
®
II Processor / Intel
®
440BX AGPset/Intel 740 Graphics
Accelerator System Block Diagram ..............................................................3-3
3-2 The Schematic Diagram for GPO27#, PCIRST# (System Reset),
RESET#, ROMA16 Signals ..........................................................................3-4
3-3 The Schematic Diagram for the WEB#, SCASB#, SRASB#,
CS0B#, CS1B# and TEST............................................................................3-5
3-4 Intel740™ Graphics Controller (On Board Device) Remains in
Low Power Mode ..........................................................................................3-6
3-5 Intel740™ Graphics Controller (On Board Device) State Diagram...............3-6
3-6 Point-to-Point Topology ................................................................................3-8
3-7 Major Signal Sections .................................................................................3-10
3-8 Example ATX Placement for a UP Pentium
®
II Processor /
Intel
®
440BX AGPset / Intel 740 Graphics Accelerator Design ..................3-11
3-9 Four Layer Board Stack-up.........................................................................3-12
3-10 Point-to-Point Topology ..............................................................................3-15
3-11 3 Device Data Load Topology.....................................................................3-16
3-12 3 Device Strobe Load Topology..................................................................3-16
3-13 3 Device Data Load Topology (Solution 1 is Shown)..................................3-17
3-14 3 Device Strobe Load Topology (Solution 1 is shown) ...............................3-17
3-15 Clock Topology and Matching.....................................................................3-17
3-16 Layout Dimensions (MA[11:0])....................................................................3-19
3-17 Layout Dimensions (MD[63:0], DQM[7:0])..................................................3-19
3-18 Layout Dimensions (WEA#, SRASA#, SCASA#, CSA0#)..........................3-20
3-19 Memory Layout Dimensions (TCLK1).........................................................3-20
3-20 Memory Layout Dimensions (RCLK and OCLK to RCLK)..........................3-21