Intel740™ Graphics Accelerator Design Guide
vii
Tables
2-1 Mix and Match Options For Intel740™ Graphics Accelerator Card..............2-2
2-2 Intel740™ Graphics Accelerator Power Supplies.........................................2-3
2-3 Bt829B GND and AGND Pins.....................................................................2-12
2-4 Bt829B VCC and AVCC Pins......................................................................2-12
2-5 Bt869 Digital and Analog Power Pins .........................................................2-13
2-6 AGP Signal Lengths....................................................................................2-13
2-7 Strobes and Corresponding Signal Groups ................................................2-13
2-8 Supported Memory Options (Other Memory Options Are
Not Supported)............................................................................................2-14
2-9 Memory Layout Restrictions (See Figure 2-12 and Figure 2-13)................2-14
2-10 Memory Layout Restrictions (See Figure 2-14 and Figure 2-15)................2-15
2-11 Memory Layout Restrictions (See Figure 2-16 and Figure 2-17)................2-16
2-12 TV Out/ROMA Trace Lengths (See Figure 2-22)........................................2-20
2-13 GPIO Functions ..........................................................................................2-21
3-1 State of Signals to be Driven After System Reset but at Least
One Clock Prior to Asserting TEST ..............................................................3-4
3-2 Signal Duration of the GPO Signals from PIIX4............................................3-5
3-3 Data and Associated Strobe .......................................................................3-13
3-4 Data Signal and Strobe Guideline Assumptions.........................................3-14
3-5 Control and Clock Signal Guideline Assumptions.......................................3-14
3-6 Data signal and strobe requirements..........................................................3-14
3-7 Control Signal Line Length Requirements ..................................................3-15
3-8 Strobe and Data Segment Solution Space .................................................3-16
3-9 Clock Segment Solution Space ..................................................................3-18
3-10 Supported Memory Options (Other Memory Options Are
Not Supported)............................................................................................3-18
3-11 Memory Layout Restrictions (See Figure 3-16 and Figure 3-17)................3-19
3-12 Memory Layout Restrictions (See Table 3-16 and Table 3-17)...................3-19
3-14 Memory Layout Restrictions (See Figure 3-19) ..........................................3-20
3-13 Memory Layout Restrictions (See Figure 3-19) ..........................................3-20
4-1 Thermal Design Considerations Chart..........................................................4-1
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