Keithley 2001 User Manual

IEEE-488 Reference
4-10
Arm Event Register  This is a latched, read-only register
whose bits are set by the Arm Condition Register and Tran-
sition Filter. Once a bit in this register is set, it will remain set
(latched) until the register is cleared by a specific clearing
operation. The bits of this register are logically ANDed with
the bits of the Arm Event Enable Register and applied to an
OR gate. The output of the OR gate is the Arm Summary Bit
that is applied to the Operation Condition Register. The fol-
lowing SCPI query command can be used to read the Arm
Event Register:
:STATus:OPERation:ARM:EVENt?
Reading this register using the above SCPI command clears
the register. The following list summarizes all operations that
will clear the Operation Event Register:
1. Cycling power.
2. Sending the *CLS common command.
(B14 - B2)
(B15)
(B1) (B0)
OR
Arm
Condition Register
Arm Event
Enable Register
Seq 1 = Sequence 1 (Set bit indicates that the
2001 is in the arm layer of Sequence 1)
&
&
0
Seq1
(B14 - B2)
(B15)
(B1) (B0)
0
Seq1
(B14 - B2)
(B15)
(B1) (B0)
0
Always
Zero
Seq1
PTR
NTR
Arm
Transition Filter
Arm Event
Register
(B14 - B2)
(B15) (B1) (B0)
Seq1
To Bit B6 (Arm) of
Operation Event
Condition Register
(See Figure 4-7).
From ORed
Summary of
Sequence Event
Status (See
Figure 4-9).
= Logical AND
= Logical OR
= Positive Transition Register
= Negative Transition Register
&
OR
PTR
NTR
F
igure 4-8
A
rm event status
3. Sending the :STATus:OPERation:ARM? query com-
mand.
Arm Event Enable Register  This register is programmed
by the user and serves as a mask for the Arm Event Register.
When masked, a set bit (B1) in the Arm Event Register will
not set the Waiting for Arm bit in the Operation Condition
Register. Conversely, when unmasked, a set bit (B1) in the
Arm Event Register will set the Waiting for Arm bit.
Bit B1 in the Arm Event Register is masked when the corre-
sponding bit (B1) in the Arm Event Enable Register is
cleared (0). When the masked bit of the Arm Event Register
sets, it is ANDed with the corresponding cleared bit in the
Arm Event Enable Register. The logic “0” output of the AND
gate is applied to the input of the OR gate and thus, will not
set the Waiting for Arm bit in the Operation Condition Reg-
ister.

Keithley 2001 Specifications

General

Brand	Keithley
Model	2001
Category	Multimeter
Language	English