IEEE-488 Reference
4-18
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:QUEStionable:PTR 65535 and
:STATus:QUEStionable:NTR 0 commands.
Questionable Event Register This is a latched, read-only
register whose bits are set by the Questionable Condition
Register and Transition Filter. Once a bit in this register is
set, it will remain set (latched) until the register is cleared by
a specific clearing operation. The bits of this register are log-
ically ANDed with the bits of the Questionable Event Enable
Register and applied to an OR gate. The output of the OR
gate is the Questionable Summary Bit (QSB) of the Status
Byte Register. The following SCPI query command can be
used to read the Questionable Event Register:
:STATus:QUEStionable:EVENt?
Reading this register using the above SCPI command clears
the register. The following list summarizes all operations that
will clear the Questionable Event Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the :STATus:QUEStionable? query command.
Questionable Event Enable Register This register is
programmed by the user and serves as a mask for the Ques-
tionable Event Register. When masked, a set bit in the Ques-
tionable Event Register will not set the Questionable
Summary Bit (QSB) in the Status Byte Register. Conversely,
when unmasked, a set bit in the Questionable Event Register
will set the QSB bit.
A bit in the Questionable Event Register is masked when the
corresponding bit in the Questionable Event Enable Register
is cleared (0). When the masked bit of the Questionable
Event Register sets, it is ANDed with the corresponding
cleared bit in the Questionable Event Enable Register. The
logic “0” output of the AND gate is applied to the input of
the OR gate and thus, will not set the QSB bit in the Status
Byte Register.
A bit in the Questionable Event Register is unmasked when
the corresponding bit in the Questionable Event Enable Reg-
ister is set (1). When the unmasked bit of the Questionable
Event Register sets, it is ANDed with the corresponding set
bit in the Questionable Event Enable Register. The logic “1”
output of the AND gate is applied to the input of the OR gate
and thus, will set the QSB bit in the Status Byte Register.
The individual bits of the Questionable Event Enable Regis-
ter can be set or cleared by using the following SCPI com-
mand:
:STATus:QUEStionable:ENABle <NRf>
The following SCPI query command can be used to read the
Questionable Event Enable Register:
:STATus:QUEStionable:ENABle?
Reading this register using the above SCPI command does
not clear the register. The following list summarizes opera-
tions that will clear the Questionable Event Enable Register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:QUEStionable:ENABle 0 com-
mand.
4.6.8 Queues
The Model 2001 uses two queues; the Output Queue and the
Error Queue. The queues are first-in first-out (FIFO) regis-
ters. The Output Queue is used to hold readings and data
messages, and the Error Queue is used to hold error messag-
es and status messages. The Model 2001 Status Model (Fig-
ure 4-5) shows how the two queues are structured with the
other registers.
Output Queue The Output Queue is used to hold read-
ings and all data that pertains to the normal operation of the
instrument. For example, when a query command is sent, the
data message that pertains to that query is placed in the Out-
put Queue.
When a data message is placed in the Output Queue, the
Message Available (MAV) bit in the Status Byte Register be-
comes set. A data message is cleared from the Output Queue
when it is read. The Output Queue is considered cleared
when it is empty. An empty Output Queue clears the MAV
bit in the Status Byte Register.
A message from the Output Queue is read by addressing the
Model 2001 to talk after the appropriate query message is
sent. The following programming example in HP BASIC 4.0
sends a query command, sends the data message to the com-
puter, and then displays it on the CRT.
10 OUTPUT 716; “*IDN?” !Request identification code.
20 ENTER 716; A$ !Address 2001 to talk.
30 PRINT A$ !Display ID code.
40 END
Error Queue The Error Queue is used to hold error mes-
sages and status messages. When an error or status event oc-
curs, a message that defines the error/status is placed in the
Error Queue. This queue will hold up to 10 messages.
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