DocID018909 Rev 11 1705/1731
RM0090 Revision history
1726
19-Oct-2012
2
(continued)
ADC:
Changed ADCCLK frequency to 30 MHz in Section 13.5: Channel-
wise programmable sampling timee.
Added recovery from ADC sequence in Section 13.8.1: Using the
DMA and Section 13.8.2: Managing a sequence of conversions
without using the DMA.
Updated AWDIE in Section 13.13.2: ADC control register 1
(ADC_CR1). Added read and write access in Section 13.13: ADC
registers.
Advanced control timers (TIM1 and TIM8):
Updated 16-bit prescaler range in Section 17.2: TIM1&TIM8 main
features.
Updated OC1 block diagram in Figure 114: Output stage of
capture/compare channel (channel 1 to 3).
Updated update event generation in Upcounting mode and
Downcounting mode in Section 17.3.2: Counter modes and
Section 17.3.3: Repetition counter.
Updated bits that control the dead-time generation in
Section 17.3.11: Complementary outputs and dead-time insertion.
Updated ways to generate a break in Section 17.3.12: Using the
break function.
Changed OCxREF to ETR in the example given in Section 17.3.13:
Clearing the OCxREF signal on an external event and changed
OCREF_CLR to ETRF in Figure 124: Clearing TIMx OCxREF.
Updated configuration for example of counter operation in encoder
interface mode in Section 17.3.16: Encoder interface mode.
Added register access in Section 17.4: TIM1&TIM8 registers.
Changed definition of ARR[15:0] bits in Section 17.4.12: TIM1&TIM8
auto-reload register (TIMx_ARR).
Updated BKE definition in Section 17.4.18: TIM1&TIM8 break and
dead-time register (TIMx_BDTR).
Table 310. Document revision history (continued)
Date Version Changes
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