Revision history RM0090
1706/1731 DocID018909 Rev 11
19-Oct-2012
2
(continued)
General purpose timers (TIM2 to TIM5):
Removed all references to “repetition counter”.
Added Figure 134: General-purpose timer block diagram.
Updated 16-bit prescaler range in Section 18.2: TIM2 to TIM5 main
features.
External clock mode 2 ETR restricted to TIM2 to TIM4 in
Section 18.3.3: Clock selection and Section 18.3.6: PWM input
mode.
Updated Section 18.3.9: PWM mode and Section 18.3.11: Clearing
the OCxREF signal on an external event.
Updated Figure 174: Master/Slave timer example to change ITR1 to
ITR0.
Updated read and write access to registers in Section 18.4: TIM2 to
TIM5 registerss.
Restored bits 15 to 8 of TIMx_SMCR as well as Table 97: TIMx
internal trigger connection in Section 14.4.3.
Removed note 1 related to OC1M bits in Section 18.4.13: TIMx
capture/compare register 1 (TIMx_CCR1).
Updated TIMx_CCER bit description for TIM2 to TIM5 in
Section 18.4.9: TIMx capture/compare enable register
(TIMx_CCER).
General purpose timers (TIM9 to TIM14):
Updated 16-bit prescaler range in Section 19.2.1: TIM9/TIM12 main
features and Section 19.2.2: TIM10/TIM11 and TIM13/TIM14 main
features.
Updated Figure 181: General-purpose timer block diagram
(TIM10/11/13/14)) to remove TRGO trigger controller output.
Added register access in Section 19.4: TIM9 and TIM12 registers
and Section 19.5: TIM10/11/13/14 registers.
Basic timers (TIM6 and TIM7):
Removed all references to “repetition counter”.
Updated 16-bit prescaler range in Section 20.2: TIM6&TIM7 main
features.
HASH:
Updated Section 25.3.1: Duration of the processing.
RNG:
Updated Section 24.1: RNG introduction.
Table 310. Document revision history (continued)
Date Version Changes
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