STMicroelectronics STM32F407 User Manual

Revision history RM0090
1712/1731 DocID018909 Rev 11
19-Feb-2013
4
(continued)
FSMC:
Updated write FIFO size in Section 36.1: FSMC main features.
Updated Figure 432: FSMC block diagram.
Updated Section 36.5.4: NOR Flash/PSRAM controller
asynchronous transactions.
Modified differences between Mode B and mode 1 in Section : Mode
2/B - NOR Flash.
Modified differences between Mode C and mode 1 in Section : Mode
C - NOR Flash - OE toggling.
Modified differences between Mode D and mode 1 in Section : Mode
D - asynchronous access with extended address.
Updated NWAIT signal in Figure 447: Asynchronous wait during a
read access, Figure 448: Asynchronous wait during a write access,
Figure 449: Wait configurations, Figure 450: Synchronous
multiplexed read mode - NOR, PSRAM (CRAM), and Figure 451:
Synchronous multiplexed write mode - PSRAM (CRAM).
Updated Table 195 to Table 214.
Updated Section : SRAM/NOR-Flash chip-select control registers
1..4 (FSMC_BCR1..4).
DEBUG
Updated Figure 483: Block diagram of STM32 MCU and Cortex®-
M4 with FPU-level debug support.
Table 310. Document revision history (continued)
Date Version Changes

STMicroelectronics STM32F407 Specifications

General

Brand	STMicroelectronics
Model	STM32F407
Category	Controller
Language	English