DocID018909 Rev 11 1713/1731
RM0090 Revision history
1726
15-Sep-2013 5
Added STM32F429xx and STM32F439xx part numbers.
Replaced FSMC by FMC added Chrom-ART Accelerator, LCD-TFT
and SAI interface.
Updated Figure 2: System architecture for STM32F42xxx and
STM32F43xxx devices.
PWR:
Updated Section 5.2.2: Brownout reset (BOR).
Added note related to CSS enabling in Entering Stop mode sections
in Section 5.3.4: Stop mode (STM32F405xx/07xx and
STM32F415xx/17xx) and Section 5.3.5: Stop mode (STM32F42xxx
and STM32F43xxx). Updated Stop mode entry in Table 27 and
Table 29.
Updated WUF bit defienition in PWR_CSR registers. Changed
CWUF and CSBF access type to ‘w’ in PWR_CR register.
RCC: Updated LSEBYP bit definition in RCC_BDCR register.
GPIOs:
Updated description of OSPEEDR bits. Removed frequency value in
description of OSPEEDR bits.Corrected typos: "IDRy[15:0]" replaced
with "IDRy" in "GPIOx_IDR" register, "ODRy[15:0]" replaced with
"ODRy" in "GPIOx_ODR" register and "OTy[1:0]" replaced with
"OTy" in "GPIOx_OTYPER" register.
DCMI: Updated Section 15.4: DCMI clocks.
IWDG: Corrected Figure 213: Independent watchdog block diagram.
RTC:
Replaced all occurrences of “power-on reset” with “backup domain
reset”. Added caution note under Table 120: RTC register map and
reset values. Changed SHPF bit type to ‘r’ in Section 26.6.4: RTC
initialization and status register (RTC_ISR)..
SPI: Updated definition of ERRIE bit in Section 28.5.2: SPI control
register 2 (SPI_CR2).
UART:
Updated Section 30.3.8: LIN (local interconnection network) mode.
Removed note in Section 30.3.13: Continuous communication using
DMA.
ETHERNET:
Modified ETH_MACA0HR (and ETH_DMABMR reset values.
Updated definitions of TSTS bit in ETH_MACSR, and TSTTR in
ETH_PTPTSSR.
Table 310. Document revision history (continued)
Date Version Changes
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