STMicroelectronics STM32F407 - Page 1714

Revision history RM0090
1714/1731 DocID018909 Rev 11
15-Sep-2013
5
(continued)
USB OTG-FS:
Removed note related to VDD range limitation below Figure 387:
OTG A-B device connection and Figure 388: USB peripheral-only
connection.
FSMC:
Updated Table 224, Table 227, Table 230, Table 234.
Replaced all occurences of DATALAT by DATLAT and SRAM/CRAM
by SRAM/PSRAM in the whole section.
Updated Section 36.1: FSMC main features. Changed bits 27 to 20
of FSMC_BWTR1..4 to reserved.
Updated Section 36.6.7: PC Card/CompactFlash operations.
Updated WREN bit in Table 226, Table 227, Table 228, Table 231,
Table 234, Table 237, Table 240, and Ta ble 244.
Updated Section 36.5.4: NOR Flash/PSRAM controller
asynchronous transactions, Section : SRAM/NOR-Flash chip-select
control registers 1..4 (FSMC_BCR1..4), Section : SRAM/NOR-Flash
chip-select timing registers 1..4 (FSMC_BTR1..4) and Section :
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4).
Updated definition of PWID in Section : PC Card/NAND Flash control
registers 2..4 (FSMC_PCR2..4).
FMC:
Updated TRDC definition in Section : SDRAM Timing registers 1,2
(FMC_SDTR1,2).
DEBUG: updated Figure 485: JTAG TAP connections.
Table 310. Document revision history (continued)
Date Version Changes