ARM Cortex A9 User Manual

Preface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. x
ID073015 Non-Confidential
ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
• ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406)
• Cortex-A9 MPCore Technical Reference Manual (ARM DDI 0407)
• Cortex-A9 Floating-Point Unit (FPU) Technical Reference Manual (ARM DDI 0408)
• Cortex-A9 NEON
®
Media Processing Engine Technical Reference Manual
(ARM DDI 0409)
• Cortex-A9 Configuration and Sign-Off Guide (ARM DII 00146)
• Cortex-A9 MBIST Controller Technical Reference Manual (ARM DDI 0414)
• CoreSight
™
PTM-A9 Technical Reference Manual (ARM DDI 0401)
• CoreSight PTM-A9 Integration Manual (ARM DII 0162)
• CoreSight Program Flow Trace Architecture Specification,v1.0 (ARM IHI 0035)
• CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual (ARM DDI
0246)
• AMBA AXI Protocol Specification (ARM IHI 0022)
• ARM Generic Interrupt Controller Architecture Specification (ARM IHI 0048)
• PrimeCell
®
Generic Interrupt Controller (PL390) Technical Reference Manual (ARM
DDI 0416)
• RealView
®
ICE User Guide (ARM DUI 0155)
• CoreSight Architecture Specification (ARM IHI 0029)
• CoreSight Technology System Design Guide (ARM DGI 0012)
• ARM Debug Interface v5 Architecture Specification (ARM IHI 0031)
Other publications
• ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic
• IEEE Std 1500-2005, IEEE Standard Testability Method for Embedded Core-based
Integrated Circuits.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design