Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-9
ID073015 Non-Confidential
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write-Through are treated as Non-Cacheable
• if ACTLR.SMP=0, all pages marked as Shared are treated as
Non-Cacheable.
ARUSER[4:0] and AW US ER[ 4:0 ] directly reflect the value of the Inner attributes and Shared
attribute as defined in the corresponding page descriptor. They do not reflect how the Cortex-A9
processor interprets them, and whether the access was treated as Cacheable or not.
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