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Level 1 Memory System

ID073015 Non-Confidential

SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

as Non-Cacheable:

• all pages marked as Write-Through are treated as Non-Cacheable

• if ACTLR.SMP=0, all pages marked as Shared are treated as

Non-Cacheable.

Note

ARUSER[4:0] and AW US ER[ 4:0 ] directly reflect the value of the Inner attributes and Shared

attribute as defined in the corresponding page descriptor. They do not reflect how the Cortex-A9

processor interprets them, and whether the access was treated as Cacheable or not.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design