ARM Cortex A9 User Manual

Performance Monitoring Unit
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-10
ID073015 Non-Confidential
0x72 Load/Store Instructions.
Counts the number of instructions being executed in the Load/Store unit. The counted instructions are still
speculative.
Approximate
0x73 Floating-point instructions.
Counts the number of floating-point instructions going through the Register Rename stage. Instructions are
still speculative in this stage.
Two floating-point instructions can be renamed in the same cycle so the event is two bits long:
b00 No floating-point instruction renamed.
b01 One floating-point instruction renamed.
b10 Two floating-point instructions renamed.
Approximate
0x74 NEON instructions.
Counts the number of NEON instructions going through the Register Rename stage. Instructions are still
speculative in this stage.
Two NEON instructions can be renamed in the same cycle so the event is two bits long:
b00 No NEON instruction renamed.
b01 One NEON instruction renamed.
b10 Two NEON instructions renamed.
Approximate
0x80 Processor stalls because of PLDs.
Counts the number of cycles where the processor is stalled because PLD slots are all full.
Approximate
0x81 Processor stalled because of a write to memory.
Counts the number of cycles when the processor is stalled. The data side is stalled also, because it is full
and executes writes to the external memory.
Approximate
0x82 Processor stalled because of instruction side main TLB miss.
Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side.
Approximate
0x83 Processor stalled because of data side main TLB miss.
Counts the number of stall cycles because of main TLB misses on requests issued by the data side.
Approximate
0x84 Processor stalled because of instruction micro TLB miss.
Counts the number of stall cycles because of micro TLB misses on the instruction side. This event does not
include main TLB miss stall cycles that are already counted in the corresponding main TLB event.
Approximate
0x85 Processor stalled because of data micro TLB miss.
Counts the number of stall cycles because of micro TLB misses on the data side. This event does not include
main TLB miss stall cycles that are already counted in the corresponding main TLB event.
Approximate
0x86 Processor stalled because of DMB.
Counts the number of stall cycles because of the execution of a DMB. This includes all
DMB instructions
being executed, even speculatively.
Approximate
0x8A Integer clock enabled.
Counts the number of cycles when the integer core clock is enabled.
Approximate
0x8B Data engine clock enabled.
Counts the number of cycles when the data engine clock is enabled.
Approximate
0x8C
NEON SIMD clock enabled.
c
Counts the number of cycles when the NEON SIMD clock is enabled.
Approximate
Table 11-6 Cortex-A9 specific events (continued)
Event Description Value

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design