Table Of Contents
Paragraph Page
Number Number
MPC5200B Users Guide, Rev. 1
TOC-10 Freescale Semiconductor
12.4.3.2 USB HC Period Current Endpoint Descriptor Register —MBAR + 0x101C ..........................................12-13
12.4.3.3 USB HC Control Head Endpoint Descriptor Register —MBAR + 0x1020 ............................................12-14
12.4.3.4 USB HC Control Current Endpoint Descriptor Register —MBAR + 0x1024 ........................................12-14
12.4.3.5 USB HC Bulk Head Endpoint Descriptor Register—MBAR + 0x1028 ..................................................12-14
12.4.3.6 USB HC Bulk Current Endpoint Descriptor Register—MBAR + 0x102C .............................................12-15
12.4.3.7 USB HC Done Head Register—MBAR + 0x1030 ..................................................................................12-15
12.4.4 Frame Counter Partition—MBAR + 0x1034 ..................................................................................................12-16
12.4.4.1 USB HC Frame Interval Register—MBAR + 0x1034 .............................................................................12-16
12.4.4.2 USB HC Frame Remaining Register—MBAR + 0x1038 ........................................................................12-17
12.4.4.3 USB HC Frame Number Register—MBAR + 0x103C ...........................................................................12-17
12.4.4.4 USB HC Periodic Start Register—MBAR + 0x1040 ...............................................................................12-18
12.4.4.5 USB HC LS Threshold Register—MBAR + 0x1044 ...............................................................................12-18
12.4.5 Root Hub Partition—MBAR + 0x1048 ........................................................................................
..................12-19
12.4.5.1 USB HC Rh Descriptor A Register—MBAR + 0x1048 ..........................................................................12-19
12.4.5.2 USB HC Rh Descriptor B Register—MBAR + 0x104C ..........................................................................12-20
12.4.5.3 USB HC Rh Status Register—MBAR + 0x1050 .....................................................................................12-21
12.4.5.4 USB HC Rh Port1 Status Register—MBAR + 0x1054 ...........................................................................12-22
12.4.5.5 USB HC Rh Port2 Status Register—MBAR + 0x1058 ...........................................................................12-26
chapter 13 BestComm
13.1 Overview .................................................................................................................................................................13-1
13.2 BestComm Functional Description .........................................................................................................................13-1
13.3 Features summary ....................................................................................................................................................13-2
13.4 Descriptors ...............................................................................................................................................................13-2
13.5 Tasks ........................................................................................................................................................................13-2
13.6 Memory Map/ Register Definitions ........................................................................................................................13-2
13.7 Task Table (Entry Table) ........................................................................................................................................13-3
13.8 Task Descriptor Table .............................................................................................................................................13-3
13.9 Variable Table .........................................................................................................................................................13-3
13.10 Function Descriptor Table .......................................................................................................................................13-3
13.11 Context Save Area ...................................................................................................................................................13-3
13.12 BestComm DMA Registers—MBAR+0x1200 ......................................................................................................13-3
13.12.1 SDMA Task Bar Register—MBAR + 0x1200 .................................................................................................13-4
13.12.2 SDMA Current Pointer Register—MBAR + 0x1204 .......................................................................................13-4
13.12.3 SDMA End Pointer Register—MBAR + 0x1208 .............................................................................................13-5
13.12.4 SDMA Variable Pointer Register—MBAR + 0x120C .....................................................................................13-5
13.12.5 SDMA Interrupt Vector, PTD Control Register—MBAR + 0x1210 ...............................................................13-6
13.12.6 SDMA Interrupt Pending Register—MBAR + 0x1214 ....................................................................................13-6
13.12.7 SDMA Interrupt Mask Register—MBAR + 0x1218 ........................................................................................13-7
13.12.8 SDMA Task Control 0 Register—MBAR + 0x121C .............................................................................
..........13-8
13.12.9 SDMA Task Control 2 Register—MBAR + 0x1220 ........................................................................................13-9
13.12.10 SDMA Task Control 4 Register—MBAR + 0x1224 ......................................................................................13-10
13.12.11 SDMA Task Control 6 Register—MBAR + 0x1228 ......................................................................................13-10
13.12.12 SDMA Task Control 8 Register—MBAR + 0x122C .....................................................................................13-11
13.12.13 SDMA Task Control A Register—MBAR + 0x1230 .....................................................................................13-11
13.12.14 SDMA Task Control C Register—MBAR + 0x1234 .....................................................................................13-12
13.12.15 SDMA Task Control E Register—MBAR + 0x1238 .....................................................................................13-12
13.12.16 SDMA Initiator Priority 0 Register—MBAR + 0x123C ................................................................................13-13
13.12.17 SDMA Initiator Priority 4 Register—MBAR + 0x1240 .................................................................................13-14
13.12.18 SDMA Initiator Priority 8 Register—MBAR + 0x1244 .................................................................................13-14
13.12.19 SDMA Initiator Priority 12 Register—MBAR + 0x1248 .....................................................................
..........13-15
13.12.20 SDMA Initiator Priority 16 Register—MBAR + 0x124C ..............................................................................13-16
13.12.21 SDMA Initiator Priority 20 Register—MBAR + 0x1250 ...............................................................................13-17
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