Address Bus Mapping
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 8-31
Figure 8-5. Address Bus Mapping (16-Bit External Data Width)
8.8.1 Example—Physical Address Multiplexing
The mapping of XL address bus to memory address bus is shown in Figure 8-4. The default mapping is:
• Row address comes from XLA[8:19]
• Column address comes from XLA[4:7, 22:29]
• Bank address comes from XLA[20:21]
Using the MT46V32M16 DDR SDRAM memory from Micron as an example, the device holds 512Mb organized as 8M x 16bit x 4banks. 2
devices are required to support the MPC5200B 32bit memory data bus, giving a total 128MB of address space (assuming just one CS
).
The Micron data sheet shows the following requirements:
• 13 row address bits
• 10 column address bits
• 2 bank select bits
XL bus address bits 30:31
control the data mask pins,
MEM_DQM[3:2].
This is an illustration of how the XL bus address enters the Memory Controller and is broken down into Row, Column, and
Bank Address fields. Shown below is the 32-bit XL bus address. The Memory Controller uses bits [27:0].
Can be used as most significant row or column address bits:
{CA13, CA112, CA11, CA9} or {CA12, CA11, CA9, RA12}
XL bus address bits 20:21 select the internal bank of a SDRAM device. Each SDRAM
device has 4 internal banks.
XL bus address bits 20:21 are presented on the MPC5200 MEM_BA[1:0] pins during
SDRAM Active, Read, and Write commands.
012345678910111213141516171819202122232425262728293031
Internal XL address bus
Ext MEM_MA pins, row
The Memory Controller extracts the Row Address from the XL bus address.
The Row Address is presented on the MPC5200B MEM_MA[12:0] pins dur-
ing SDRAM Active commands.
Row Address bit 12 depends on the Control register hi_addr bit.
1211109876543210
0 8 9 10 11 12 13 14 15 16 17 18 19
Internal XL address bus
Ext MEM_MA pins, row
12 11 10 9
8
76543210
7 8 9 10 11 12 13 14 15 16 17 18 19
hi_addr = 0
hi_addr = 1
The Memory Controller extracts the Column Address from the XL bus address. The Column Address is presented on the
MPC5200B MEM_MA[12:0] pins during SDRAM Read and Write commands.
Column Address bits 12:8 depend on the Control register hi_addr bits. Auto Precharge (MEM_MA[10])is always inhibited
(0).
External MEM_MA pins, column
Internal XL address bus
1211109876543210
6 0 7 2223242526272829305
hi_addr = 0
11
External MEM_MA pins, column
Internal XL address bus
1211109876543210
5 0 6 2223242526272829304
hi_addr = 1
11
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