Freescale Semiconductor MPC5200B - Interrupt ED Structure

MPC5200B Users Guide, Rev. 1
12-4 Freescale Semiconductor
Host Controller Interface
Figure 12-4. Interrupt ED Structure
Figure 12-5 shows a sample interrupt endpoint schedule. The schedule shows:
• two endpoint descriptors at a 1ms poll interval
• two endpoint descriptors at a 2ms poll interval
• one endpoint descriptor at a 4ms poll interval
• two endpoint descriptors at an 8ms poll interval
• two endpoint descriptors at a 16ms poll interval
• two endpoint descriptors at a 32ms poll interval.
NOTE
Unused interrupt endpoint placeholders are bypassed and the link is connected to the next available
endpoint in the hierarchy.
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Interrupt
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Endpoint Poll Interval (ms)
Interrupt
Headpointers