Freescale Semiconductor MPC5200B - ATA Multiword DMA Timing 2 Register-Mbar + 0 X3 A14; ATA Ultra DMA Timing 1 Register-Mbar + 0 X3 A18

ATA Register Interface
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 11-5
11.3.1.6 ATA Multiword DMA Timing 2 Register—MBAR + 0x3A14
11.3.1.7 ATA Ultra DMA Timing 1 Register—MBAR + 0x3A18
Bits Name Description
0:7 dma_t0 Multiword DMA cycle time. Count value is based on system clock operating frequency.
8:15 dma_td Multiword DMA read/write (DIOR/DIOW) asserted pulse width. Count value is based on
system clock operating frequency.
16:23 dma_tk Multiword DMA read/write (DIOR/DIOW) negated pulse width. Count value is based on
system clock operating frequency.
24:31 dma_tm CS
[0], CS[1] valid to DIOR/DIOW. Count value is based on system clock operating
frequency.
Table 11-6. ATA Multiword DMA Timing 2 Register
msb 012345678 9 1011121314 15
R dma_th dma_tj
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R dma_tn
Reserved
W
RESET:0 00000000 0 0 0 00 0 0
Bits Name Description
0:7 dma_th Multiword DMA write (DIOW) data hold time. Count value is based on system clock
operating frequency.
8:15 dma_tj Multiword DMA read/write (DIOR/DIOW) asserted pulse width. Count value is based on
system clock operating frequency.
16:23 dma_tn CS
[0], CS[1] hold. Count value is based on system clock operating frequency.
24:31 — Reserved
Table 11-7. ATA Ultra DMA Timing 1 Register
msb 012345678 9 1011121314 15
R udma_t2cyc udma_tcyc
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R udma_tds udma_tdh
W
RESET:0 00000000 0 0 0 00 0 0