MPC5200B Users Guide, Rev. 1
11-14 Freescale Semiconductor
ATA Register Interface
11.3.3.4 ATA Drive Features Register—MBAR + 0x3A64
11.3.3.5 ATA Drive Error Register—MBAR + 0x3A64
Table 11-22. ATA Drive Features Register
msb 012345678 9 1011121314 15
R
Reserved
WData
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved
W
RESET:0 00000000 0 0 0 00 0 0
Bits Name Description
0:7 Data Register content is command dependent. Contents become command parameters when the
ATA drive command register is written.
8:31 — Reserved
Table 11-23. ATA Drive Error Register
msb 01234 5 678 9 101112131415
R Data ABRT Data
Reserved
W
RESET:0 0000 0 000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved
W
RESET:0 000000000000000
Bits Name Description
0:4 Data Register content is command dependent. Contents become command parameters when the
ATA drive command register is written.
Register content is valid when BSY and DRQ bits are set to 0 and ERR bit is set to 1 in the
ATA drive status register. Register content is not valid when drive is in sleep mode.
5 ABRT Bit is set to 1 to indicate requested command has been aborted, because command code or
a command parameter is invalid or some other error occurred.
0:7 Data Register content is command dependent. Contents become command parameters when the
ATA drive command register is written.
Register content is valid when BSY and DRQ bits are set to 0 and ERR bit is set to 1 in the
ATA drive status register. Register content is not valid when drive is in sleep mode.
8:31 — Reserved
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