Freescale Semiconductor MPC5200B - XL Bus Arbitration Priority

Application Information
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-67
10.6.3 XL bus Arbitration Priority
When the XL Bus Arbiter Master Priority Register (Section 16.2.11, Arbiter Master Priority Register (R/W)—MBAR + 0x1F68) is set
to any configuration except all-master fair-share (all masters have the same priority), live lock can occur on the shared PCI bus and the XL
Bus, which results in system-wide live lock.
The only resolution that guarantees that this live lock scenario will not occur is to set all the XL Bus Arbiter master priorities to be equal.
Additionally, it is usually preferable that all master priorities are not set to zero, as this can generate an interrupt by the XL Bus Arbiter, if
enabled.