Freescale Semiconductor MPC5200B - Gps Gpio Simple Interrupt Open-Drain Emulation Register -Mbar + 0 X0 B

MPC5200B Users Guide, Rev. 1
7-42 Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24
Bit Name Description
0:7 SIGPIOE Individual bits to enable each Interrupt GPIO pin (pins are scattered).
bit 0 controls GPIO_SINT_7 (ETH_16 pin)
bit 1 controls GPIO_SINT_6 (ETH_15 pin)
bit 2 controls GPIO_SINT_5 (ETH_14 pin)
bit 3 controls GPIO_SINT_4 (ETH_13 pin)
bit 4 controls GPIO_SINT_3 (USB1_9 pin)
bit 5 controls GPIO_SINT_2 (PSC3_8 pin)
bit 6 controls GPIO_SINT_1 (PSC3_5 pin)
bit 7 controls GPIO_SINT_0 (PSC3_4 pin)
0 = disabled for GPIO use (default)
1 = enabled for GPIO use
8:31 — Reserved
Table 7-30. GPS GPIO Simple Interrupt Open-Drain Emulation Register
msb 012345678 9 101112131415
RSIODe
Reserved
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved
W
RESET:0 00000000 0 0 0 00 0 0
Bit Name Description
0:7 SIODe Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 0 controls GPIO_SINT_7 (ETH_16 pin)
bit 1 controls GPIO_SINT_6 (ETH_15 pin)
bit 2 controls GPIO_SINT_5 (ETH_14 pin)
bit 3 controls GPIO_SINT_4 (ETH_13 pin)
bit 4 controls GPIO_SINT_3 (USB1_9 pin)
bit 5 controls GPIO_SINT_2 (PSC3_8 pin)
bit 6 controls GPIO_SINT_1 (PSC3_5 pin)
bit 7 controls GPIO_SINT_0 (PSC3_4 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
8:31 — Reserved