Freescale Semiconductor MPC5200B - Fec Descriptor Group Address 1 Register-Mbar + 0 X; Fec Descriptor Group Address 2 Register-Mbar + 0 X

FEC Registers—MBAR + 0x3000
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 14-25
Note: X: Bit is not reset and must be initialized.
14.5.18 FEC Descriptor Group Address 1 Register—MBAR + 0x3120
The GADDR1 register is written by the user. This register contains the upper 32bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. This register must be initialized.
Note: X: Bit is not reset and must be initialized.
14.5.19 FEC Descriptor Group Address 2 Register—MBAR + 0x3124
The GADDR2 register is written by the user. The GADDR2 register contains the lower 32bits of the 64-bit hash table used in the address
recognition process for receive frames with a multicast address. This register must be initialized.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R IADDR2
W
RESET:X XXXXXXXX X X X XX X X
Bits Name Description
0:31 IADDR2 The lower 32bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address.
• Bit 31 contains hash index bit 31.
• Bit 0 contains hash index bit 0.
Table 14-27. FEC Descriptor Group Address 1 Register
msb 012345678 9 1011121314 15
R GADDR1
W
RESET:X XXXXXXXX X X X XX X X
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R GADDR1
W
RESET:X XXXXXXXX X X X XX X X
Bits Name Description
0:31 GADDR1 The GADDR1 register contains the upper 32bits of the 64-bit hash table used in the address
recognition process for receive frames with a multicast address.
• Bit 31 contains hash index bit 63.
• Bit 0 contains hash index bit 32.
Table 14-28. FEC Descriptor Group Address 2 Register
msb 012345678 9 1011121314 15
R GADDR2
W
RESET:X XXXXXXXX X X X XX X X