Freescale Semiconductor MPC5200B - GPS Simple GPIO Open Drain Type Register -MBAR + 0 X0 B08

General Purpose I/O (GPIO)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 7-33
7.3.2.1.3 GPS Simple GPIO Open Drain Type Register —MBAR + 0x0B08
24:27 PSC2 Individual enable bits for the 4 Simple GPIO on PSC2 port.
bit 24 controls GPIO_PSC2_3 (PSC2_3 pin)
bit 25 controls GPIO_PSC2_2 (PSC2_2 pin)
bit 26 controls GPIO_PSC2_1 (PSC2_1 pin)
bit 27 controls GPIO_PSC2_0 (PSC2_0 pin)
0 = Disabled for GPIO (default)
1 = Enabled for GPIO
28:31 PSC1 Individual enable bits for the 4 Simple GPIO on PSC1 port.
bit 28 controls GPIO_PSC1_3 (PSC1_3 pin)
bit 29 controls GPIO_PSC1_2 (PSC1_2 pin)
bit 30 controls GPIO_PSC1_1 (PSC1_1 pin)
bit 31 controls GPIO_PSC1_0 (PSC1_0 pin)
0 = Disabled for GPIO (default)
1 = Enabled for GPIO
Table 7-23. GPS Simple GPIO Open Drain Type Register
msb 012345678 9 101112131415
R
Reserved IRDA ETHR Reserved USB
W
RESET:0 00000000 0 0 0 00 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R
Reserved PSC3 PSC2 PSC1
W
RESET:0 00000000 0 0 0 00 0 0
Bit Name Description
0:1 — Reserved
2:3 IRDA Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 2 controls GPIO_IRDA_1 (IR_USB_CLK pin)
bit 3 controls GPIO_IRDA_0 (IRDA_TX pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
4:7 ETHR Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 4 controls GPIO_ETHI_3 (ETH_11 pin)
bit 5 controls GPIO_ETHI_2 (ETH_10 pin)
bit 6 controls GPIO_ETHI_1 (ETH_9 pin)
bit 7 controls GPIO_ETHI_0 (ETH_8 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
8:11 — Reserved
Bit Name Description